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Abstract: Thin (<4nm) Physical Vapor Deposited (PVD) Ru-10at.% Ta films were evaluated as diffusion barriers and seed enhancement layers for Cu metallization in sub 25nm trenches. The ratio of Ru/Ta on blanket wafers could be influenced by changing the process conditions. However, a difference in Ru/Ta ratio did not influence the thermal stability of the layers during High Temperature X-ray Diffraction (HT-XRD) measurements as all RuTa films exhibited good thermal properties since no Cu-silicide formation was observed for temperatures below 500°C. The RuTa films also passed an 85°C/85% relative humidity (RH) test of one week of storage in order to test the H2O barrier integrity of the films. Furthermore no difference was found when testing the O2 barrier integrity during 300s anneals at various temperatures between 250°C and 500°C. Good Cu fill of 20nm trenches (AR 4:1) patterned in oxide was achieved when combining the RuTa films with PVD Cu seed layers with thicknesses ranging from 7 to 20nm and Cu plating. When compared to a Ta(N)/Ta barrier, relatively high electrical yields (60–80%) were obtained for structures with CDs <30nm when combining RuTa films with PVD Cu seed layers as thin as 7nm (on field), hence evidencing the seed enhancement ability of these layers. [Copyright &y& Elsevier]

Abstract: In this paper we will highlight key integration issues that were encountered during the development of the 3D-stacked IC Through Silicon Via (TSV) module and present solutions to achieve a robust copper TSV. Electrical performance of the obtained TSV module is discussed based on a lumped RC model for 3D ring oscillators containing TSVs between bottom and top tiers. [Copyright &y& Elsevier]