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Flip-chip interconnects made entirely from copper are promising candidates to overcome the intrinsic limits of solder-based interconnects and match the demand for increased current densities of high-performance microprocessors. To this end, dip-based all-copper interconnects have been demonstrated to be a viable approach to form electrical interconnects by sintering copper nanoparticles between the copper pillar and pad. However, the performance of this technology is limited by residual porosity of the copper joint formed between the pillar and the pad during sintering. Moreover, the applicability of this technology in the printed circuit board industry is constrained by thermomechanical stresses that arise from the sintering. Furthermore, the compatibility of the sintering approach with standard finishing layers used as diffusion-barrier layers to provide wetting and to prevent the oxidation of the pillar and pad surfaces is unknown. In this paper, we pursue the advancement of dip-based all-copper interconnect technology. We demonstrate the robustness of dip-transfer of copper paste for varying withdrawal velocities and typical nonuniformities in copper pillar heights. Moreover, we prove the applicability of this technology with fine pillar diameters and pitches down to 10 and $20~\mu \text{m}$ , respectively. In addition, we demonstrate reduced porosities of the copper joints by applying pressure during the bonding process at 200 °C. This densification leads to interconnects with four times the shear strength and half the electrical resistance compared to interconnects formed without the application of pressure. In addition, the bonding temperature is decreased to 160 °C by applying a novel copper paste formulation, reducing the thermomechanical stress in the assembly caused by the cooling from the sintering temperature. Finally, the compatibility of this technology with EPAG, ENIG, and ENEPIG finishing layers is demonstrated, with resulting shear strength of the interconnects above 70 MPa and electrical resistance comparable to the unfinished samples.

Pastes based on copper (Cu) nanoparticles (NPs) are promising electronic-packaging materials for the attachment of high-power devices. However, the rapid oxidation of nanostructured Cu requires the use of reducing agents during processing, which makes it less suitable for attaching large-area dies (> 4 mm2). Recently, the functionalization of Cu-NP surfaces with a mixture of amines prevented oxidation, allowing for sintering without the need for reducing agents. Here we investigate the sintering mechanisms involved during die attachment using pastes of passivated Cu NPs, with particular focus on the critical role of the carrier solvents. Using 1-nonanol or 1-decanol as solvents, we first demonstrate the absence of Cu-oxide phases in the pastes after fabrication and the stability of the resulting nanostructured copper for as much as 30 min in air. By measuring the evolution of the electrical characteristics of the paste during drying and sintering, we show that electrically conductive agglomerates form among the NPs between 141°C and 144°C, independent of the carrier solvent used. The carrier solvent was found to affect mainly the densification temperature of the copper agglomerates. Because they lead to uniform sintering of the material, Cu pastes based on solvents with a low boiling point and high vapor pressure are preferable for attaching dies with area greater than 25 mm2. We show that dies with an area as large as 100 mm2 can be attached using a Cu paste based on 1-nonanol. These pastes enables the formation of temperature-resistant bonding for high-power devices using a simple and cost-effective approach.

The current feed capacity of electrical interconnects is mainly limited by the poor electromigration (EM) resistance of lead free-solder interconnects. Thus, the community investigates alternative interconnect approaches and materials, e.g. all-copper interconnects using copper pastes. EM is an electron scattering based transport of metal atoms, occurring at high current densities, resulting in voids and thus finally leads to an open interconnect. For all-copper interconnects, it is expected that the maximum current density could be increased, while power losses can be mitigated, due to the higher EM resistance and reduced resistivity of copper compared to solder, respectively. However, all-copper interconnects formed by copper pastes applied without pressure result in a porous copper interconnect morphology with unknown EM performance. Thus, the authors report on results of EM tests on nanoporous copper films. The investigated copper paste is especially designed to be used for flip chip interconnects and contains nano and micron sized copper particles. Paste films were performed by doctor blading, followed by a sintering process at 200°C in formic acid. SEM analysis on FIB cross-sections of sintered films revealed the fusion of the nanoparticles to a nanoporous, sponge like morphology with embedded microparticles. Furthermore, a porosity of approximately 30% could be identified. The high porosity results in a non deterministic electrical network with a measured effective resistivity of ~10 μΩ cm, which is five times higher than the one of bulk copper (1.78 μΩ cm). For detailed investigations of the EM characteristics a setup, as well as a specific test sample layout were designed and implemented. The setup is capable to feed a current of up to 40 A to eight serial samples in a temperature range from room temperature to 250°C in ambient atmosphere. The test samples consist of copper lines, relief printed onto a silicon based carrier substrate, to bridge a 200 μm wide gap between two electrochemically deposited copper electrodes. The voltage drop across the copper line can be measured while driving the current through the line, by four point probing. In addition, a platinum based thermocouple (PT1000) is implemented on the carrier substrate beneath the nanoporous copper. It allows to prove the temperature of the nanoporous copper, to derive exact test conditions and the temperature coefficient of resistance of the nanoporous copper. Initial tests of samples exposed to elevated temperatures above 90°C, but without any current applied, resulted in the resistance increase of the nanoporous copper due to oxidation. Accordingly, a photoresist coverage was applied on the copper lines to mitigate the copper oxidation to levels acceptable for EM testing. A series of EM tests were then performed under constant current conditions to derive the EM kinetics and to explore the damage mechanisms. At current densities of 1 MA/cm^2 and a sample temperature of 90°C, the observed ‘time to failure’ of the nanoporous copper was more than six times higher than the one of tin based lead free solder. Furthermore, the authors will summarize their findings of the EM study performed on the nanoporous copper.

The introduction of wide-band-gap semiconductors such as silicon carbide (SiC) in power electronic devices has allowed operation temperatures beyond 300°C. However, these high operational temperatures are not suitable for traditional die-attach materials such as solder. Therefore, a bonding material that is stable beyond 300°C, with high electrical and thermal conductivities and low cost is essential. In this regard, copper (Cu) nanoparticle-based pastes are promising candidates due to their stability at high temperatures and elevated thermal and electrical conductivities. Furthermore, the recent introduction of oxide-free Cu pastes based on amine-passivated Cu nanoparticles enables these materials to be processed in inert atmosphere.We report here on attaching SiC dies to direct-bonded copper ceramic substrates by sintering oxide-free Cu pastes. Applying bonding pressure during sintering improves the die-attach quality by reducing the percentage of residual voids and increasing shear strength. We succeeded in further reducing the percentage of voids by using a paste containing a solvent with a low boiling point and high vapor pressure. Furthermore, we developed a novel dual-layer process to deposit Cu paste that yields residual percentages of voids in the die attach as low as 5% and a shear strength of 29 MPa. Finally, the reliability of the die attach by oxide-free Cu paste was investigated with thermal shock cycling.

The solder alloys applied in state-of-the-art flip-chip electrical interconnects are one of the main limits to improving the high power handling of this technology. To overcome this issue, the replacement of solder with interconnects purely made from copper is desirable, owing to copper's superior electromigration resistance with respect to solder. Recently, dip-based all-copper interconnects were shown to be a promising approach to form all-copper flip-chip interconnects by the sintering of Cu nano -and microparticles between copper pillars and pads. In this process, the Cu particles are applied on the pillar tips by a dip-transfer method and then collapsed onto pads, forming an assembly. Then, the assembly is sintered for 30 min in a thermal oven under constant flow of formic-acid-enriched nitrogen. After the sintering, copper joints that connect the pillars and pads are formed, resulting in the so called "dip-based all-copper interconnects". Despite the large interest raised around this approach, the requirement of formic-acid application and the long sintering time limits its scalability. In our work, we report the first example of dip-based all-copper interconnects formed by laser sintering, without the application of formic acid and with a process time of only a few seconds. These results could lead to the development of a novel ultrafast and formic-acid free assembly technique of all-copper flip-chip interconnects.

Flip-chip interconnects made entirely from copper are needed to overcome the intrinsic limits of solder-based interconnects and match the demand for increased current densities. To this end, dip-based all-copper interconnects are a promising approach to form electrical interconnects by sintering copper nanoparticles between the copper pillar and pad. However, the remnant porosity of the copper joint formed between the pillar and the pad limits the performance of this technology. Moreover, the applicability of this technology in the printed circuit board (PCB) industry is endangered by thermo-mechanical stresses that arise during the sintering and by the unknown compatibility with standard finishing layers used to prevent the oxidation of the copper. This work reports three main advances in dip-based all-copper interconnect technology. First, a reduction in the porosity level of the copper joint is obtained by application of pressure during the bonding. Second, a decrease of the bonding temperature to 160 °C is achieved. Third, the compatibility of this technology with standard finishing layers is demonstrated.

Copper is the metal of choice for electrical circuits in electronics. It is lower in cost than silver and offers excellent electrical properties like low electrical resistivity and electromigration resistance. Physical vapor deposition and wet-chemical etching or electroforming are the standard processes used to deposit and pattern copper on silicon and in printed-circuit-board technology. Recently, copper inks and pastes have become available for the printing of copper films, with the potential outcome of lowering the production cost beyond that of the established processes. Furthermore, the printing processes are compatible with role-to-role fabrication, and are hence attractive for flexible electronics. In this study, a bi-modal copper paste containing nano- and micro-particles is transferred in a relief printing process by using silicon stamps. It was possible to demonstrate electrical conductive tracks with a linewidth down to 8 μm. The spacing between neighboring tracks is related to their width and can be as low as 10 μm. It was possible to achieve a sheet resistance of less than 8 mΩ sq–1 after formic-acid-assisted sintering at 180 °C. The low sintering temperature enables the direct placement of electronic components without additional soldering and thus saves time and production costs.