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The back-end components of integrated circuits (ICs) are susceptible to self-heating deteriorating effects due to the microscale interconnects carrying large current densities, and thus require innovative passive cooling strategies. This article investigates the cooling effect of the high conductivity metallization (MET) fill that is used in conjunction with the chemical mechanical planarization (CMP) process. Thermal simulation models are developed for a three-level back end of line (BEOL) stack and then validated experimentally using high-resolution thermal imaging. A coupled approach is used to optimize the numerical model and fully characterize the BEOL embedded passive cooling solution. Results indicate that stricter thermal constraints are present for devices higher in the BEOL stack and exhibit the highest cooling potential from the use of CMP fill in the underlying MET layers. As a thermal improvement strategy for such thermally critical interconnects, a CMP fill-based cooling solution is presented by modifying the fill pattern in order to maximize heat dissipation within the BEOL. The resulting heat spreader (HS) design achieved up to 30% reduction in temperature for 10- $\mu \text{m}$ -wide interconnects and can reach 43% for narrower interconnects. The gained cooling makes it possible to extend the activation limits of interconnects by 15% and 25%, respectively. The experimentally validated HS simulation model is used to conduct parametric analysis for a range of interconnect dimensions with an eye on standardizing the HS design within the BEOL stage of ICs. [ABSTRACT FROM AUTHOR]