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In this chapter, we have discussed the design and implementation of current-steering DACs for wideband applications. Different structures have been outlined and for high-speed and high-resolution applications we have found the segmented DAC structure to be most suitable. A key design issue is to find the proper number of bits encode into a thermometer code or if multi-segmented structures are needed. We have shown how the performance of the converter depends on errors in the layout by comparing two similar DACs and highlighted the importance of high frequency poles in the output impedance of the unit current sources. We have shown that it is possible to reach an SFDR of over 75 dBc in a standard 3.3 V digital CMOS process and an SFDR of 65 dBc with a single 1.5-V supply voltage.

In this chapter we have discussed two important analog functional blocks in data converters, the MDAC and the integrator. Both SC and SI circuits were considered. We showed how to calculate the noise and maximum speed of the circuits based on first order models. The maximum speed of the circuits is determined by the bandwidth and the required number of clock phases. The maximum speed normally decreases as the gain of the circuit increases. The thermal noise of the circuits can be referred to the input as a noise voltage. We showed that the noise voltage power for all the circuits is only determined by the capacitors in the circuit.

In this chapter we have discussed the time-interleaved ADC. The performance is limited by mismatches between the channels. Gain and offset errors can be calibrated. A more severe problem is the phase skew errors which increases at high signal frequencies. The most effective way to reduce these errors is to use an input S/H circuit which usually needs an opamp that runs at the full speed of the ADC. The opamp is therefore difficult to design and power consuming. An improved global passive sampling technique that does not need an opamp was introduced. The limitations of the technique was also discussed. The phase skew distortion can be reduced by 10 to 20 dB compared to not using a global sampling technique.

In this chapter we have discussed oversampling sigma-delta converters. They are suitable for high resolutions but the high oversampling ratio (OSR) limits the signal bandwidth. To increase the signal bandwidth cascaded modulators have been discussed. Gain errors in the integrators cause leakage of low order quantization noise at the output which limits the resolution of the converter. The integrator gain errors need not be as accurate as the full resolution and converters with up to 15 – 16 bit have been successfully implemented without calibration. To further reduce the quantization noise in the modulator a multi-bit quantizer can be used in the last stage of the converter. For a single stage modulator a multi-bit quantizer would require calibration since the DAC linearity directly limits linearity of the OSADC. For cascaded modulator however, the signal in the last stage has a weak correlation to the input signal and linearity errors in the multi-bit DAC will cause noise, not distortion. In addition to this the DAC linearity error is noise shaped, which significantly reduces the required linearity of the DAC. We have also discussed SC implementations of oversampled sigma-delta converters and investigated some of the most important limitations and how they affect the performance of the modulator. Based on the discussions and design example was presented.