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Although the number of cores is increasing continuously in modern microprocessors for applications such as HPC and AI, the available power is strictly limited by the thermal power budget. To overcome this limitation, recently, each core has been implemented with a dedicated integrated voltage regulator to increase the efficiency of power usage. Distributed digital LDO (DLDO) is a powerful solution for the integrated voltage regulator because it can supply uniform power over the entire core with reduced IR drop and help the thermal management [1– 4]. In the previous distributed DLDOs [1– 3], even though all LDO outputs are connected to drive the power-delivery network, the LDOs operate independently using their own controller, which occupies a large portion of the LDO size. Therefore, the current density in these types of structures is low. In [4], the distributed DLDO uses a dual-loop structure. In this scheme, the high current density can be achieved because the four shared global controllers control the 16 local LDOs (LLDOs) for highly accurate regulation. However, the LLDOs consume large quiescent current since they operate at a switching frequency of several-GHz for a fast transient response. Besides, the load current range is narrow due to the small switching duty-cycle range of the power FETs. Because of these drawbacks, the structure proposed in [4] has limitations in practical applications.

A DC-DC converter, which tracks minimum power loss under various conditions, is presented in this paper. With this DC-DC converter, a new approach for optimum efficiency, which implements theoretical equations intactly at the circuit level, was adopted. This approach has high reliability against process variation. The concept of lossless soft-switching was also adopted in discontinuous-conduction-mode (DCM) operation. The proposed DC-DC converter has a maximum power efficiency of 91% at the switching frequency of 1 MHz. The proposed converter is able to maintain a maximum power efficiency of around 90% over the whole range of input voltage from 2.9 to 4.5 V and output voltage from $-$ 3.8 to $-$ 5.9 V. This chip is implemented in a 0.35 $\mu$ m BCD process and occupies an area of 2.1 $\times $ 1.4 mm $ ^{2}$ .

This paper proposes a new control scheme of zeroth-order control (ZOC) for PWM DC-DC converters in which the pole frequencies of the control loop are no longer dependent on the values of the inductor, output capacitor, or the output load current. In the proposed scheme, the output voltage of the converter is regulated by a comparator. The main control loop of the converter regulates the inductor energy which is built up to an optimum value to be delivered to the output by means of the time interval between the rising edge of the main switch driving pulse and the comparator output pulse. A boost DC-DC converter with the proposed ZOC has been implemented and fabricated in a commercial 0.35 μm BCDMOS process. A maximum efficiency of 88% is achieved at a total output power of 480 mW with the switching frequency of 833 kHz when the input voltage and the output voltage are 3.7 V and 8 V, respectively. Over 85% efficiency is maintained for a wide range of the output load current from 40 mA to 300 mA.

This paper presents a new control scheme dubbed Bang-Bang Zeroth-Order Control (BBZOC) for Single Inductor Multiple Output (SIMO) buck converter. The main loop control utilizes a phase detector, charge pump, filter, and comparator. The SIMO buck converter with BBZOC simplifies the compensation design compared to conventional voltage mode control. This work is fabricated in 1P4M 0.35um BCD process and achieves 83% maximum efficiency with the rated output power of 1.04W. The maximum output power is 2.7W and the maximum power density is 1.07 W/mm2. Considering the difference in the process, this work represents the state of the art in the power density.

This paper introduces an on-chip controller without off-chip components to reduce controller size for use as a Zero-Order-Control converter (ZOC). DC offset error by adding sawtooth signal in ZOC is self-corrected using a new control scheme, so as to overcome weak point of ZOC. This controller is applicable to both buck and boost, but a boost converter is chosen for verification here. A 0.35μm BCD process is used for chip with controller area of 0.791mm2. An efficiency of 90% is obtained for an 8 V output from 3.7 V at 480mW with 926 KHz.

A variety of controllers are used in DC-DC converters. Among them, voltage-mode control and current-programmed-mode control are widely used in industrial applications. In such controllers, however, values of inductor, output capacitor, and/or load condition usually affect loop stability and limit the performance of switching converter. Recently, load-independent-control (LIC) method is reported, where freewheeling current is fed back to overcome such a limitation [1]. While this is a viable solution in principle, it still has a vulnerable aspect that must be addressed: the feedback control is affected by the level of freewheeling current and an extra power switch is needed for freewheeling current flow which lowers power efficiency. Another LIC method using vestigial current control is reported in [2]. The weak points of vestigial control are that it needs an auxiliary output and power is consumed in steady state to regulate vestigial current. In this paper, we present a zero-order-controlled (ZOC) boost DC-DC converter that has a robust control loop and does not consume any extra power in the steady state.