Search

The Cuk inverter operating in continuous conduction mode (CCM) is susceptible to grid disturbances and its transfer function has two right-half plane zeros, which cause a large phase lag. To improve the output-tracking precision in the grid-connected environment, a repetitive controller with linear phase-lead compensation has been developed for the Cuk inverter. However, this controller requires heavy computational burden and memory space; these problems become more severe as the converter operates at a higher switching frequency. This paper proposes to use a down-sampled repetitive controller (DRC) for Cuk CCM inverter to alleviate these problems. The down-sampling technique itself can significantly reduce the computational burden and memory space of RC. On the contrary, its control accuracy becomes very low, particularly for the Cuk CCM inverter. Unlike conventional module integrated inverters (MIIs), the Cuk CCM inverter must adopt a fractional-order phase-lead compensation algorithm to compensate for the effect of the large phase lag in the down-sampled environment. To clarify the inevitable usage of DRC with a fractional-order phase-lead compensation for Cuk CCM inverter, the DRC is classified into four types, this paper provides its detailed design guideline based on stability analysis of the overall control system and also presents design examples for representative MIIs. Experiments using a 300-W prototype Cuk inverter validate that the proposed control approach achieves acceptable output-tracking accuracy. The total computation time and memory space with the DRC decrease by 76.0% and 80.0% compared to those with the conventional RC while the output-tracking accuracy with the DRC decreases by 0.42%.

A robust optimized active disturbance rejection control (ADRC) based grid voltage sensorless current controller is developed for an LCL -filtered grid-connected inverter (GCI) via a predictive control approach under various sources of disturbance, including the model uncertainties, the LCL inherent resonance phenomenon, and nonideal grid environment. Aiming to improve the sinusoidal reference tracking performance as well as to reject lumped sinusoidal disturbances in the control practice, a resonant extended state observer is integrated into the ADRC structure, which guarantees a rigorous stable operation of inverter for bounded filter parameter uncertainties and adverse grid voltage conditions. The grid frequency adaptability is thoroughly considered in the controller design process and synchronization technique, offering an extra capability for GCI to operate under different grid voltage frequency levels or even the frequency deviation caused by grid fault events. Robustness against parameter uncertainty and system stability is analyzed through the discrete-time frequency analysis and pole-zero map approaches. The simulation and hardware experiments are conducted for GCI with LCL filter parameters designed for two typical regions (i.e., the resonance frequency is less and greater than one-sixth of switching frequency) to validate the theoretical analysis and the effectiveness of the proposed control method.

Series resonant converter-unfolding inverter (SRCUI), a pseudo-dc-link inverter based on series resonant converter, is a promising topology featuring high efficiency and high step-up operation capabilities, which are important for many applications interfacing with renewable energy systems. Out of the existing modulation methods for SRCUI, variable-frequency modulation (VFM) tends to be the most efficient due to complete zero voltage switching (ZVS), but it suffers from limited modulation range. This limitation leads to distortion in the output waveform near zero crossing points. To extend the effective range of VFM and reduce the distortion, a technique termed sequential waveform synthesis (SWS) is proposed in this article. SWS is specifically created for input-parallel-output-series multimodular inverter based on SCRUIs. It activates/deactivates each module sequentially, so the remaining active modules have higher individual output voltage and power that assist in ZVS. The total output voltage waveform synthesized by individual output voltages has lower distortion and retains soft-switching function. The principle of SWS is explained in this article by using total harmonic distortion as a performance indicator. In addition, the modeling and controller design of variable-frequency-modulated SRCUI are also addressed since they were hardly studied before. The controller and the concept of SWS are implemented on a multimodular inverter prototype formed by three SRCUIs and verified by the experimental results.

Discontinuous conduction mode (DCM) and critical conduction mode (CRM) have held dominant positions in low-power boost power factor correction (PFC) control. Typically, two-level DCM and CRM suffer from high peak current and variable frequency at several-hundred kilohertz, respectively. The two factors can cause secondary effects such as high electromagnetic interference, current stresses, input filter design difficulty, and switching losses. Only to take merits of DCM and CRM that are fixed frequency and lower peak current, this article utilizes three-level boost (TLB) and its three-level current-slope options. This article proposes a hybrid conduction mode (HCM) control, which adopts adaptive single-switch on -time to achieve fixed-frequency quadrangular CRM operation. At lower input voltage, low inductor current enters DCM so that TLB PFC experiences hybrid operation modes depending on varying ac input. Analyses and experiment results in this article confirm that the proposed HCM control can achieve huge reductions of switching losses and peak current stress, improving efficiency in wide-range input voltage and load at the cost of acceptable PF drop. Moreover, a simple voltage-balancing scheme is implemented to the proposed control and verified effective to resolve the inherent topology issue.

In this article, we present a bridgeless hybrid-mode Zeta inverter for distributed energy systems. We integrate the secondary diode of the conventional unfolding-type Zeta inverter into one of diagonal pairs of the secondary-side switches in a bridgeless Zeta inverter. This structure decreases the number of active power components and provides naturally well distributed loss at the body diodes of the secondary-side switches over one cycle of grid voltage, and as a result, increases both output power transfer and reliability. To attain medium-high power capacity with appropriate size of magnetic components, the bridgeless Zeta inverter operates in both discontinuous conduction mode (DCM) and continuous conduction mode (CCM). However, control of the proposed inverter is difficult because of the distinct system dynamics caused by the operations in DCM and CCM. To deal with this control problem, we first identify the mode boundaries and, corresponding to each mode, develop a dynamic model to design a controller. Then, we propose to use a feedback controller plus a feedforward controller supplemented with a repetitive controller that uses a phase-lead compensator. Experimental results using a 300-W prototype demonstrate the feasibility and effectiveness of the proposed modeling and control approach.

This article proposes an average periodic delay-based repetitive controller for power factor correction (PFC) converters undergoing grid frequency variations. When the grid frequency is changed, a conventional repetitive controller requires an interpolation method or additional memory to achieve frequency adaptability. Furthermore, frequency adaptability can also be realized using a variable sampling frequency; however, this requires additional computation effort and a multirate digital control system. In this article, with a fixed sampling frequency and memory length, the proposed repetitive controller, which generates the average periodic delay unit, maintains its harmonic compensation performance under grid frequency variations. In the proposed method, the control variables are updated depending on the phase of the grid voltage to reflect the grid frequency deviations in the average period delay unit. Because no complicated software modification is necessary, the proposed scheme can be easily plugged in the existing control algorithm. The theoretical analysis and stability issues of the proposed scheme have been discussed in detail to ensure stable operation and disturbance rejection. Both the simulations and the experiments on a 1.5-kW PFC converter have been carried out to verify the effectiveness of the proposed repetitive control.

This article presents a single-sourced hybrid binary-cascaded multilevel inverter (BCMLI) with front-end high-frequency-link (HFL) converters. The purpose of HFL converters is to boost a dc-source voltage to three bus voltages in a binary ratio. In this article, one of the HFL converters is removed from the system and the voltage of the floating capacitor caused by the removal is controlled by a newly proposed floating-capacitor-voltage (FCV) control. Compared with the conventional BCMLI, the system size and cost can be significantly reduced while maintaining promising features, including 15-level output, high voltage gain, galvanic isolation, and reactive-power capability remain unchanged. The proposed FCV control utilizes one of the switching angles at the voltage-level transitions as the control variable in a single-loop design, which facilitates control simplicity in the proposed system. The hybrid BCMLI with the proposed FCV control shows relative advantages of voltage gain, isolation capability, reactive supply, and simple control system over the state-of-the-art hybrid inverter topologies with FCV control methods. The details of the hybrid BCMLI, modulation schemes, proposed FCV control design, and comparative assessment are included in this article. In order to validate the proposed system and FCV control, a set of experiments with a 1-kW BCMLI prototype has been conducted for wide-range load levels and power factors.

This brief presents a unified voltage balancing feedforward (UVBFF) for three-level boost (TLB) power-factor-correction (PFC) circuit in discontinuous and critical conduction modes. In general, the topology in both modes puts emphasis on low-cost system. Thus, electrolytic capacitors with wide-tolerance are commonly used at outputs and voltage unbalance is inevitable even under symmetric operations of two boost cells. In this brief, three-level switching capability of TLB PFC is introduced and asymmetric on-time feedforward for main switches is proposed. The proposed UVBFF can be realized by a single equation and harmonized with conventional feedback voltage-loop so that easy implementation is the key merit. The effectiveness of UVBFF is proven by analyses and experimental results.

Traditionally, standalone closed-loop drain–source sensed synchronous rectification (SR) implementation has been limited by the voltage limits of commercial IC controllers. Commercially available SR controllers have low maximum voltage limits, necessitating a high-voltage blocking mechanism for use in higher voltage rectifiers. Therefore, in this article, a board-level blocking method to protect drain–source voltage sensed SR controllers from high voltage and currents at the board level is presented. This method allows for the high-voltage operation of drain–source SR controllers. This method is self-biasing and allows for SR controller operation far beyond the datasheet voltage limits (kV+). The mechanisms of operation are analyzed, and design criteria created for selecting an optimal clamp is proposed. The proposed solution is simple and low in cost and component count, making closed-loop, cyclically adaptive SR a practical solution for high-voltage rectifiers. The blocking circuit is presented, analyzed, and tested for use with commercially available drain–source SR controller integrated circuits (ICs). Hardware SR testing is completed on two LLC-DCX (dc-transformer) modules with 300 V, and over 1-kV output voltages to demonstrate the voltage blocking capabilities.

The low-voltage ride through condition (LVRT) attracts wider attention with the increased power of central grid-connected photovoltaic (PV) systems. The conventional double-loop-based control strategy designed for the nominal voltage is slow and potentially unstable under the LVRT operation. In this article, a novel sliding-mode control-based feedback linearization is proposed to improve response speed of the PV system under LVRT condition. To increase the robustness of the control to parameter variations, sliding-mode control is combined with the feedback linearization in this article. Further, the complete linearization of the PV system can be achieved over the whole operating range. Moreover, the dc-link voltage operating point of the PV panel can be dynamically adjusted based on the drop depth of the grid voltage, which will reduce the load changes during the LVRT and subsequently ensure the ac current levels to stay within the design limits in any fault situation and enhance the LVRT capability of the central grid-connected PV system. Finally, a 100-kW PV inverter is built to validate the feasibility and effectiveness of the proposed strategy for LVRT.

In inductive power transfer systems, impedance matching is critical in obtaining high efficiency. However, since the load impedance is subject to variations in most applications, especially wireless charging, maintaining impedance matching is a challenge. One valid solution is to maintain the equivalent load impedance at the optimal value against load variations by controlling a load-side power converter. Nonetheless, the system overall cost, size, and complexity can be increased. In this article, based on a proper selection between full-bridge and half-bridge modes of the inverter and rectifier, an operation mode selection method is proposed that can achieve semi-impedance-matching with large load variations. In general, with the proposed method, high overall efficiency can be obtained while neither additional power converters nor complicated control is required. A 1-kW prototype has been developed and the experimental results have verified the proposed method.

Conventional critical conduction mode (CRM) control for many boost-derived power factor correction (PFC) circuits forms triangular inductor current. For three-level boost (TLB) converter, the conventional method is unattractive because losses increase but waveform quality remains unchanged, compared to other topologies. In order to obtain higher efficiency and improved waveform qualities, this article focuses on the distinctive structure of TLB and its inherent degree-of-freedom (DOF) in current-slope shaping. Based on the DOF, a new CRM control for TLB PFC is proposed and analyzed. Detailed design and digital implementation method are also provided. Different from conventional methods, the proposed CRM control divides each switching cycle into three parts including common on -time of two switches, additional on -time of one switch and common off -time. Accordingly, TLB inductor current is synthesized in quadrangular forms. The analyses and experimental results confirm that switching frequency and peak input current of TLB can be reduced by the proposed control. Due to the reductions, efficiency, total harmonic distortion, and quality of input current are improved with practically unchanged power factor.

Magnetic characteristics of a switched reluctance motor (SRM) determine the modeling accuracy, the performance of a position sensorless control, and the torque ripple reduction control. Due to double saliency structure and core saturation, the magnetic characteristics of SRM is dependent on both the rotor position and the winding current amplitude, which makes it difficult to measure the actual incremental inductance or flux linkage. This article presents the magnetic characteristics identification method. A quad current sampling technique is proposed to capture the derivative of the winding current at a specific rotor position and current amplitude. The flux linkage, co-energy, and torque are calculated from the obtained incremental inductance profile. The proposed method can be easily implemented on digital signal processor–based SRM drive without any extra circuit. The LCR meter and torque sensor measurements are provided to validate the proposed incremental inductance measurement method.

In this article, an optimal design procedure of shunt RC damped LCL filter is discussed. The proposed design procedure finds the minimum damping resistance to guarantee the stability of the grid-current controller without affecting the effectiveness of the filter. This minimum value is derived using the factorized filter input admittance and filter forward transadmittance. The proposed factorization procedure allows us to have an analytical expression of system poles and zeros. Moreover, the minimum damping resistor is determined upon the desired crossover frequency and the desired phase margin of the grid-current controller. After that, an objective function is assumed, and an optimization problem is formulated to minimize the physical size of the filter by minimizing the total capacitance and inductance and by minimizing the filter ripple content as well. Accordingly, the proposed objective function minimizes the filter physical size and filter power losses and, hence, enhances filter's efficiency. A prototype demonstrates and validates the proposed filter design and analysis experimentally.

Pad misalignments are almost inevitable in most inductive power transfer (IPT) systems. It tends to cause parameter variations and, thus, significantly affects the performance of the IPT system. In this article, a hybrid IPT system with misalignment tolerance using the quadruple-D quadrature pads (QDQPs) is proposed to tolerate the x , y , z , and diagonal misalignments with load-independent output voltage, simplifying or even canceling control schemes. Besides, the proposed approach can restrict the increase of the primary current when the secondary side moves out of the operating region. Moreover, a new parametric design method is presented according to the misalignment characteristics of QDQPs. The method can limit the output voltage fluctuation to a certain range, given a predetermined misalignment distance. A 3.5-kW prototype was built to verify the proposed hybrid IPT system. The primary and secondary coil sizes are 400 mm × 400 mm, and the air gap is 150 mm. Experimental results demonstrate that the proposed hybrid system can tolerate −150 to +150 mm x -misalignment, −150 to +150 mm y -misalignment, −20 to +35 mm z -misalignment, and −100 to +100 mm diagonal misalignment with load-independent output voltage. Within the predetermined misalignment range, the output voltage fluctuation is less than 5%.

This paper presents a bridgeless Cuk-derived single power conversion inverter with reduced number of power components, which has reactive-power capability. The secondary diode of the conventional unfolding-type Cuk inverter is integrated into one of the secondary-side switches in the bridgeless Cuk-derived configuration, which reduces the number of active-power components. A modulation technique is developed to provide a current path during reverse power flow; this technique enables operations under unity and nonunity power factors. A repetitive controller coupled with a linear feedback controller and a feed-forward controller are used to achieve accurate output current tracking under the harsh control environment. Driving the diode-integrated switch in synchronous rectification mode provides higher power conversion efficiency than that under diode-based secondary side rectification. Circuit operation and design guidelines of the bridgeless Cuk inverter are presented in detail. A 500-VA prototype inverter was fabricated to demonstrate the desirable performance of the bridgeless Cuk-derived inverter.

In the no-load condition, LLC converter usually fails to regulate its output voltage although it operates at a high switching frequency. Till now, it is hard to obtain the exact relationship between design parameters and the maximum switching frequency for no-load regulation capability. In this paper, a specific criterion for no-load regulation of LLC converter is provided, without using active components or other modulation schemes. By analyzing the macroscopic switching period and microscopic switching transition in the no-load condition, it is shown that not only the peaking resonant current during the switching transition, but also the resonant tank design affect the no-load regulation of the LLC converter, which affects the no-load regulation capability. Furthermore, the relationship among design parameters is analyzed and the design guideline is also provided to achieve no-load regulation at the specified maximum switching frequency. To verify the effectiveness of the proposed design, 400 V input and 50 V/200 W output prototype is built and tested.

Coupled-inductor buck converters are more effective in high step-down applications compared to conventional buck converters given the same circuit complexity. A coupled-inductor buck converter can adopt synchronous conduction mode to fully mitigate turn-on loss and operate at high frequency. However, this typically induces large circulating currents and harms the converter's light-load efficiency. To alleviate these issues, this paper analyzes the mechanisms behind synchronous conduction mode and then proposes a dual-loop control method solution. The variable-frequency outer loop of the proposed control minimizes conduction and deadtime loss, while the voltage-mode-controlled inner loop provides the necessary output voltage regulation. Experiments are conducted with a compact prototype converter using switching frequencies higher than 2 MHz, and the prototype is verified under load transients to validate both control loops. The results show that the light-load efficiency can be boosted by more than 8%.

A 12-pulse converter has been commonly used for a large-scale power generating system. The arrangement of a delta–delta (Δ–Δ) and a delta–wye (Δ–Y) phase-shift transformer pair in series with the voltage source eliminates undesirable harmonics from nonlinear loads. Recently, a novel front-end for a multi-generator power system was proposed, which utilizes a single Y–Δ transformer to shunt between the two 30° phase-shifted generator outputs and results in the comparable harmonic elimination performance to the conventional 12-pulse rectifier. The shunt-type Y–Δ transformer front-end achieves more than 75% transformer size reduction, making it extremely attractive to large-scale industrial and shipboard applications. However, the exact 30° phase shift between the two rotating generators can drift in a practical system, especially under dynamic conditions. The harmonic performance under the non-ideal 30° phase-shift condition can deteriorate with the Y–Δ shunt-type front-end. To understand the impact of non-ideal phase-shifted generator sources, this paper derives the mathematical models through the use of an equivalent circuit, a square-wave analysis, and the phasor representation to show the harmonic cancellation principle and verifies the results with the computer simulation.

This paper proposes a modified bridge switch-type flux-coupling nonsuperconducting fault current limiter (BSFC-NSFCL) for suppressing the fault current and voltage sag. A flux-coupling reactor and a bidirectional bridge switch are combined to perform the functions of steady-state line current sharing and fault current suppression. The modified BSFC-NSFCL mainly utilizes the magnetic flux cancellation effect to make the limiter behave as a short circuit on the circuit during normal operation. Hence, there is almost no impact on the power system when the limiter is used. When a fault event occurs, the bridge switch turns off immediately, and then, the magnetic flux cancellation effect disappears. Thus, the impedance of primary coil inserts into the circuit to restrict the fault current and voltage sag phenomena. Once the fault is removed, the bridge switch turns on again, and the BSFC-NSFCL recovers to the normal operation. The modified NSFCL is more cost-effective and easy to be implemented than the flux-coupling superconducting fault current limiter. Theoretical analysis for the BSFC-NSFCL has been fully developed and proven by MATLAB software. Finally, the analytical, simulated, and experimental results have been carried out to verify the feasibility and performance of the proposed BSFC-NSFCL.

This paper presents a dual-mode Cuk inverter for photovoltaic/thermoelectric power applications. A dual-mode Cuk inverter operates in both discontinuous conduction mode (DCM) and continuous conduction mode (CCM), and has the advantages of low ripples of voltage and current at the input and output, medium power density, and step-up/step-down ability, but is difficult to control because DCM and CCM have distinct system dynamics. To overcome this control problem, we propose to use a repetitive controller (RC) with a multiple phase-lead compensator for the dual-mode Cuk inverter. If the RC is applied by itself, the distinct system dynamics may severely degrade its system performance. Thus, in the proposed RC, we mainly use a multiple phase-lead compensator to compensate for the different phase lags of the dual-mode Cuk inverter. To reduce the burden from the RC, we use the dual-mode nominal duty ratio as feedforward control input. We also analyze the boundary of operation modes in the dual-mode Cuk inverter, then provide detailed and practical guidelines to design the control parameters. Experimental results obtained on a 500-W digitally controlled module integrated converter prototype confirmed the effectiveness of the control approach.

Current control loop response in voltage source inverters impacts the quality of output current and output voltage waveforms. Parabolic current control provides a fast transient response with approximate-constant switching frequency, solving the frequency variation problem of hysteresis current control. This makes it a good candidate for the current control loop of voltage source inverters to achieve a good system performance. Yet, parabolic current control is often implemented with digital-to-analog converters, analog comparators, and field-programmable gate array circuits where increasing switching frequency pushes update speed and bandwidth requirements. Concurrently, even if the transient response of parabolic current control is fast, it can still take up several switching cycles converging to steady state. In order to solve both problems, a new current control strategy, motivated by the convergence analysis of parabolic current control but with a convergence process that takes just one switching operation, is proposed: single-step current control. Since single-step current control samples two data points in a switching cycle instead of using continuous parabolic carriers, it can be easily implemented in a digital microcontroller then high switching frequency can be achieved. The small signal model, dead-time compensation, and stability analysis are also studied in this paper. The convergence speed of the algorithm is verified with experimental hardware prototype and the transient performance of the designed voltage source inverter meets expectation.

This paper proposes an iterative learning control (ILC) scheme for a dual-mode flyback inverter operating in both discontinuous conduction mode (DCM) and continuous conduction mode (CCM). In dealing with more than 200-W power applications, the dual-mode flyback inverter takes advantage of both DCM and CCM operations. However, it is difficult to control the output current because the system gain is quite low in DCM and the system transfer function has a right-half plane zero in CCM. To overcome the problems occurring in DCM and CCM operations, we propose an ILC scheme with multiple phase-lead compensation. The ILC is proposed to achieve accurate reference tracking and to reject periodic disturbances. The multiple phase-lead compensation technique is then employed to compensate for the effect of different system dynamics. As a theoretical result, we derive the asymptotic stability of the closed-loop system. We also performed the numerical simulations and experimental tests to validate the proposed control approach.

A control scheme for stand-alone inverters that utilizes an inductor current observer (ICO) is proposed. The proposed method measures disturbance load currents using a current sensor and it estimates the inductor current using the ICO. The filter parameter mismatch effect is analyzed to confirm the ICO’s controllability. The ICO and controllers are designed in a continuous-time domain and transferred to a discrete-time domain with a digital delay. Experimental results demonstrate the effectiveness of the ICO using a 5-kVA single-phase stand-alone inverter prototype. The experimental results demonstrate that the observed current matches the actual current and that the proposed method can archive a less than 2.4% total harmonic distortion (THD) sinusoidal output waveform under nonlinear load conditions.

A front-end for multi-generator power system was recently proposed, which utilizes a single wye-delta (Y-Δ) transformer to shunt between the two 30° phase-shifted generator outputs. The shunt type phase-shift transformer front-end provides comparable 5th and 7th harmonic elimination performance to the conventional 12-pulse rectifier with more than 75% transformer size reduction. In this paper, a hybrid front end, which consists of the shunt Y-Δ transformer and an active power filter is proposed to further improve the power quality. In this configuration, 11th and 13th harmonics from nonlinear load are actively compensated by the active power filter and 5th and 7th harmonics are trapped by Y-Δ transformer. Theoretically, the performance of the proposed front end is equivalent to a traditional 24-pulse rectifier with a significant reduction in the overall size and weight, which makes it attractive to large-scale industrial and shipboard applications. The harmonic cancellation principle of the proposed front end is derived and verified by simulation and experimental results.

This paper presents small-signal modeling of three-level boost (TLB) converter for active front-end power-factor-correction in medium-voltage (MV) solid state transformer (SST). The analysis has been conducted for continuous conduction mode (CCM) in two different voltage modes of TLB to derive system dynamics and to confirm that transfer functions in the voltage modes are identical to one another. Based on the derived models, this paper introduces MV-SST system design guidelines including controller and input filter, considering limited selection width of off-the-shelf high-voltage-rating capacitors and nontrivial source impedances. Digital feedback controller and input filters are designed based on the derivations and implemented to a 4-module-stacked SST system prototype of which TLB plays a role of active front-end PFC. In order to verify the effectiveness of small-signal analysis and system design, experimental verifications of the prototype have been conducted for single phase 3.8-kV rms input voltage to 400-V de bus voltage conversion and 15-kW full load condition in the existence of 65-mH source impedance.

Switched reluctance motor (SRM) has double saliency structure and operates under the saturated condition to achieve high energy conversion ratio. Therefore, the magnetic characteristics of switched reluctance motor is highly non-linear that the actual inductance profile can not be simply obtained by the inductance measurement instrument. As the control performance of SRM drive is highly dependent on a priori knowledge of magnetic characteristics, the accurate measurement is important. This paper presents the incremental inductance measurement method through closed loop current control. The rate of change of the phase current is captured by additional sampling instant. The effects of phase resistance variation, core loss, and power device voltage drop are considered to minimize the measurement error. The measurement results are verified with LCR meter and torque transducer measurement.

Tapped-inductor (TI) buck converter is capable of high step-down conversion with extended duty cycle over traditional buck converter. Additionally, its synchronous conduction mode (SCM) can completely eliminate turn-on losses, allowing high switching frequency operation and subsequent high power density. Nevertheless, the converter efficiency under SCM is refrained by circulating current and therefore a dual-loop (DL) control is proposed in this paper. Based on a time-domain model for zero-voltage-switching (ZVS) process, the DL control has a variable-frequency (VF) outer loop to minimize both ripple-current conduction loss and dead-time loss. While the VF loop moderately adjusts switching frequency, an inner voltage-mode-control (VMC) loop regulates output voltage. To verify the idea, a MHz-level, 15-W, DL-controlled TI buck prototype is built. Experimental results demonstrate the efficiency-boosting effect of the VF loop especially under light load. Finally, the derived plant model of TI buck converter under VMC is introduced in the paper along with the feedback design for output regulation.

This paper analyzes CCM/DCM operations of three-level boost (TLB) converter and derives ideal duty-ratios for feedforward control in power factor correction (PFC) applications. The analyses are conducted for two different TLB operation modes characterized by input voltage range. Since duty-ratio feedforward is a widely used technique to improve PFC transient responses and mitigate the burden of feedback control, accurate duty-ratio computations for all possible operation modes and conduction modes are necessary. By comparing the derived duty-ratios for CCM and DCM regions, current conduction modes of TLB can be detected in real-time and proper duty-ratio feedforward with minimum duty-ratio selection can be provided. The experimental results by a 500 W prototype of TLB PFC rectifier are provided in order to verify the effectiveness of the derivations and feedforward technique.

This paper proposes a memory space adjustable repetitive controller (RC) for an unfolding-type isolated Cuk inverter operating in the continuous conduction mode (CCM). To achieve acceptable tracking performance with reduced computation burden and memory space, we use the memory space adjustable RC in addition to the proportional-integral (PI) controller and the feedforward controller. Two right-half plane (RHP) zeros in the transfer function of the Cuk CCM inverter cause phase lag of the closed-loop control system. To compensate for the phase lag accurately under the low-sampled environment, we develop a fractional-order phase-lead compensator in the memory space adjustable RC. Simulation and experimental tests using a 300-W unfolding-type Cuk CCM inverter have verified the proposed controller achieves desirable performance.

In this paper, the low voltage stress of switches, high voltage gain DC-DC converter is proposed. The operating principle of the converter is similar to that of the conventional buck converter. Therefore, the proposed converter can be operated in the discontinuous conduction mode, continuous conduction mode, depending on the design. Moreover, the controller is also similar to that of the traditional buck converter, results in the simple controller. Furthermore, the voltage stress of every switch is reduced significantly compared with the conventional converter. Therefore, the use of the low voltage rating switches reduces the losses significantly. A 200W converter prototype is successfully built and tested to verify the feasibility of the proposed converter.

This article proposes an improved odd-harmonic repetitive controller (IORC) for a Cuk-derived inverter. The IORC is composed of a modified structure of an odd-harmonic repetitive controller (ORC) combined with a proportional-integral (PI) controller and a feedforward controller to achieve a zero steady-state error in the Cuk-derived inverter. The IORC features much larger gains at odd-harmonic frequencies by modification of an existing ORC, so both its convergence rate and transient response become much faster. The added benefit of using the IORC is that it has wider bandwidth at odd-harmonic frequencies, so it is more insensitive to the grid frequency fluctuation. The IORC also adopts a linear phase-lead compensator to compensate for the phase lag of the Cuk-derived inverter. Hence, the IORC can effectively eliminate the odd-harmonic components in the output current of the grid-connected Cuk-derived inverter while using less memory space. However, the distinctive structure of the IORC makes it difficult to guarantee the stability of the overall control system. Thus, in this article, a new stability analysis method is developed for the IORC system, and then a practical design guideline is also provided to obtain the optimal control parameters. Experimental results are presented to validate the proposed controller in the 300-W Cuk-derived inverter prototype.

Increasing usage of high output voltage, low output current resonant-based DC-DC converter systems can face a stability issue when cycle-by-cycle drain-source synchronous rectification (SR) controllers are paired with low RDS, on rectifier switches. A current resonance phenomenon can be observed at low power conditions within the LLC resonant converter. This instability can lead to inconsistent SR operation, excessive conduction loss, output ripple, and poor light-load efficiency. In this paper, the issue is root caused, simulated, and an FPGAbased duty cycle rate limiter is built and tested to verify a possible method of alleviating the issue.

This paper investigates the effects of low frequency harmonics and source impedance on active front-end rectifier in modular solid-state transformer. The topology for analysis was selected to three-level boost (TLB) converter which is widely used for power factor correction. Harmonic contents of input source cause periodic distortions in input current, degrading THD factor. In the presence of finite source impedance, performance of properly designed current controller can be deteriorated in terms of phase margin and system instability. In this paper, those external effects are studied with equivalent single module TLB. Repetitive controller and input filter designs are presented to compensate periodic distortion and overlapped impedance interaction in frequency domain, respectively. Simulation and experimental results are provided to verify the analysis.

A position sensorless control method for switched reluctance motors from standstill to running without pre-stored magnetic characteristics is proposed. For startup, diagnosing pulses are injected into all three phases, and the current magnitudes of all phases are examined to estimate the rotor position. Additionally, a phase current vector method is applied to eliminate the risk of locked-rotor and startup hesitations. In running condition, diagnosing pulses are injected to two non-torque productive phases to estimate the position and commutation instant. An angle tracking observer estimates the continuous angle from the acquired discrete position information. The proposed method does not require any prior knowledge of the switched reluctance motor except the pole configuration. Therefore, memory storage for magnetization curves of a switched reluctance motor is not needed. The experimental results show a hesitation-free startup, a good speed reference tracking, and an accurate position estimation performance under different load conditions.

This paper, proposes the design approach to achieve fast transient response for the current-mode adaptive on-time control circuit of an on-chip buck converter. The major difference between the current-mode with and without adaptive on-time control circuits is the on-time generation circuit. The sample and hold transfer function of the current-mode adaptive on-time control circuit can obtain the fixed double poles system without a high Q at half the switching frequency. The current-mode adaptive on-time control circuit needs to design the current sense gain properly to obtain a large bandwidth with the appropriate phase margin to achieve a fast transient response. The 5-V input, 1.2-V and 1-A output on-chip buck converters with and without the current-mode adaptive on-time control circuit are implemented to verify the superiority of the adaptive on-time control through computer simulation and hardware experiments.

In this paper, improvement of the transient response of voltage-mode controller with the ripple-based circuit for an on-chip buck converter is proposed. The main purpose of the proposed circuit is to enhance the load transient response while maintaining the system stability. For the ripple-based circuit, a low-pass filter is used to generate a voltage signal similar to the inductor current waveform. This voltage signal is then injected into the voltage feedback with a bypass capacitor. Such a ripple-based control circuit can prevent instability caused by the output ceramic capacitors for buck converters. Because the voltage-mode controller does not require the current sensor, it can allow elimination of quiescent current caused by the current-mode controller and avoid the current sensor bandwidth limitation, which tends to result in high frequency distortion. This paper will discuss the design methodology of voltage-mode controller using ripple-based circuit for an on-chip buck converter. An on-chip 5-V input, 3.3-V and 1-A output ripple-based buck converter control is simulated and implemented with hardware prototype to verify the transient response improvement and stable operation during load step-up and - down dynamics.

A 12-pulse rectifier with the combination of $\Delta-\Delta$ and $\Delta-$ Y type phase-shift transformers has been commonly used for harmonic cancellation in a large-scale power system. Recently a shut phase-shift transformer was suggested to have the same harmonic cancellation effect with more than 75% size reduction over the traditional phase-shift transformers provided that the power generation system equips with multi-generator that can be regulated with 30° phase difference between the two sources. Theoretically, the harmonic trapping performance of a shunt configuration is equivalent to 12-pulse rectifier with a significantly reduced transformer rating and size. However, the working condition and the performance of a shunt phase-shift transformer rectifier under the practical condition have not been verified. This paper presents a detailed analysis of a harmonic elimination principle of a shunt phase-shift transformer through an equivalent circuit model and a mathematical derivation. The analysis also describes the working condition for a shunt phase-shift transformer rectifier and the effect of phase difference of generators on the harmonic cancellation performance. The derived model is verified with computer simulation under the ideal and non-ideal 30° phase-differential configurations.

In this paper, the ac small signal modeling technique for both pulse-width-modulation (PWM) current and speed controller of SRM drive system is presented. With the small signal modeling for linearization of the SRM, the output transfer function in both PWM current loop and speed loop can be obtained. Both PI current controller and PI speed controller can be also designed with sufficient stability margin by using the small signal model. A criterion for selection of proportional and integral (PI) controller for an SRM is also proposed. In order to simultaneously reduce acoustic noise and torque ripple, a specific current profile was applied to SRM drives with proposed current and speed controller. A hardware prototype of 12/8, three-phase 2kW SRM with TMS320F28335 was constructed and tested. The criteria for selection of PI controller is applied to the SRM Drive system. Torque ripple and acoustic noise in both cases of traditional square current waveform and the modified current profile are compared. The experimental results indicate that the proposed method for derivation of optimized gains can lead to reduced acoustic noise and improve the dynamic performances of the SRM drive system.

In this paper, a controller design methodology is proposed for a CLLLC -type bidirectional resonant converter. The soft switching of all devices in this topology and the very high operating frequency lead to increased overall system efficiency. However, the dynamic nature of this converter is highly dependent on loading conditions, which proves challenging when designing the voltage and current closed-loop controllers. System instability is mainly due to the high-Q resonant peaking, which is observed in the open-loop bode-plots. In this paper, the controller design methodology is proposed, which accounts for the dynamics behavior due to load variations. The controller stability will be evaluated against the entire range of operating switching frequency. Both battery charging and regeneration modes will be described and analyzed. The focal contribution of this paper will focus on defining the worst operating scenarios for the converter using system-level modeling and analysis. In addition, the controller will be defined based on these operating points. To validate and verify the controller design methodology proposed, a 3.5-kW converter is designed with the appropriate output voltage and current loop controllers. The step response verified a stable system designed and thus proving the proposed controller design methodology.

Hysteresis current control is an attractive nonlinear current-control method for voltage source inverters when a fast system response is required. A well-known disadvantage of hysteresis current control is that the system has to operate over a wide switching frequency range. This causes an increase in the switching losses of the system and increases the difficulty in designing the output filter. The recently proposed parabolic current control solves this problem by employing a pair of parabolic carriers as the control band. Through the use of parabolic current control, constant switching frequency can be achieved. In the implementation of parabolic current control, dead time is employed to prevent shoot through of the inverter leg. The employment of dead time impacts the current-tracking precision and the stability range of the parabolic current-control method. Another side effect of using dead time is that the switching frequency deviates from the desired value. In this paper, the effects of dead time on parabolic current control are analyzed, and a compensation method is proposed for voltage source inverters that use parabolic current control. Using the output current direction of the voltage source inverter, a new pair of improved parabolic carriers is derived. As a result, the current error can be well controlled and the effects of dead time can be eliminated. The improvement in the current tracking of the system comes with an added benefit where the duty cycle range is extended. The effectiveness of the proposed dead-time compensation method is experimentally verified by the use of a full-bridge voltage source inverter.

A buck converter operated in synchronous — conduction-mode (SCM) can obtain zero-voltage-switching (ZVS) of both switches without any auxiliary components, which is beneficial for high-switching frequency operation. To obtain ZVS of high-side switch, buck converter requires adequate dead-time duration and reverse inductor current. Through the law of conservation of energy, minimum reverse inductor current required for ZVS can be calculated accurately by a modified method. On top of the modified method, a ZVS model based on resonance is proposed in this paper. The proposed method also leads to accurate ZVS condition but with more information within the transition. The principle and application of the proposed resonant model are interpreted by a comparative example. Moreover, simulation waveforms and hardware testing results of a 1 MHz/30 W SCM buck converter prototype are presented for verification.

There are two commonly used 3-phase configurations in power grid applications, the 3-phase 3-wire, and 3-phase 4-wire configurations. The 3-phase 4-wire power converter systems is necessary to supply single-phase loads but at the expense of higher output harmonics and losses, as compared to 3-phase 3-wire systems. The neutral inductor is added to reduce the neutral line harmonics and a LCL+ L filter is adopted for 3-phase 4-wire high power density converter (HPDC) systems. A toroidal nanocrystalline cored inductor is included in the neutral line with the objectives to reduce high frequency output harmonics and improve the efficiency of HPDC. The LCL+L filter has been designed, simulated and verified experimentally.

The design of a digital state-space controller employing a deadbeat state observer is presented for uninterruptible power source (UPS) inverter applications with inductor-capacitor (L-C) filters. Conventionally, the inductor current and capacitor voltage values are utilized as the measured feedback variables for the controller, and the load current is either measured or estimated. In the proposed method, the inductor current sensor is not used, and an output load current sensor is used. The proposed state-space controller utilizes the estimated current and voltage states from an observer as the feedback values, and the measured output load current information as the feedforward value. The advantage of the proposed method is that the measured load current information accurately compensates the observer and control system pole deviation due to the load current variation, and thus it increases the overall system robustness with only one current sensor. The proposed control scheme exhibits low total harmonic distortions and fast transient responses. Experiments are performed on a UPS prototype to demonstrate the effectiveness of the proposed scheme.

This paper proposes a pulsewidth-modulation strategy to achieve balanced line-to-line output voltages and to maximize the modulation index in the linear modulation range where the output voltage can be linearly adjusted in the multilevel cascaded inverter (MLCI) operating under unbalanced dc-link conditions. In these conditions, the linear modulation range is reduced, and a significant output voltage imbalance may occur as voltage references increase. In order to analyze these effects, the voltage vector space for MLCI is evaluated in detail. From this analysis, the theory behind the output voltage imbalance is explained, and the maximum linear modulation range considering an unbalanced dc-link condition is evaluated. After that, a neutral voltage modulation strategy is proposed to achieve output voltage balancing as well as to extend the linear modulation range up to the maximum reachable point in theory. In the proposed method, too large of a dc-link imbalance precludes the balancing of the output voltages. This limitation is also discussed. Both the simulations and the experiments for a seven-level phase-shifted modulated MLCI for electric vehicle traction motor drive show that the proposed method is able to balance line-to-line output voltages as well as to maximize the linear modulation range under the unbalanced dc-link conditions.

This paper presents the benefits of interleaving three phase voltage source converters (VSCs) to improve the power density. The output harmonics are also analyzed in frequency domain, then design and optimization of coupled inductor and output filter are given. Verifications are carried out through electrical circiut and electromagnetic's FEM simualtions. Finally, the inductor weight are compared with and without interleaving.

This paper presents a new overall control strategy for small-scale wind energy conversion systems (WECS). The purpose of the proposed strategy is to utilize a maximum power point tracking control (MPPT) to maximize the captured energy when the wind speeds are below the rated speed. For high wind speed region; two stall controllers are developed: The constant speed stall controller which will limit the rotational speed of the generator to its rated value, and the constant power stall controller, which will regulate the captured power to be within the system rating. For the MPPT control, a modified perturb and observe (P&O) algorithm is utilized, where the dc side current is used as a perturbation variable and the dc-link voltage slope information is used to enhance the tracking speed and stability of the algorithm. For the speed and power regulation operation during high wind speeds, the system is controlled in the stall region to limit the rotational speed and the power of the generator. A stabilizing control loop is proposed to compensate for the stall region instability. A new mode transfer control strategy is developed to effectively control the transition between different modes of operation while ensuring the system stability without using any preknowledge of the system parameters. A 1 kW hardware prototype is developed and tested to validate the proposed new control strategy.

This paper proposes a maximum power point tracking (MPPT) algorithm for small-scale wind energy conversion systems. The proposed algorithm uses the dc current as the perturbing variable. The algorithm detects sudden wind speed changes indirectly through the dc-link voltage slope. The voltage slope is also used to enhance the tracking speed of the algorithm and to prevent the generator from stalling under rapid wind speed slowdown conditions. The proposed method uses two modes of operation: A perturb and observe (P&O) mode with adaptive step size under slow wind speed fluctuation conditions, and a prediction mode employed under fast wind speed change conditions. The dc-link capacitor voltage slope reflects the acceleration information of the generator, which is then used to predict the next step size and direction of the current command. The proposed algorithm shows enhanced stability and fast tracking capability under both high and low rate of change wind speed conditions and is verified using a 1.5 kW prototype hardware setup.

This paper analyzes the effect of the admittance component for the digitally controlled single-phase bridgeless power factor correction (PFC) converter. To do this, it is shown how the digital delay effects such as the digital pulse-width modulation (DPWM) and the computation delays restrict the bandwidth of the converter. After that, the admittance effect of the entire digital control system is analyzed when the bridgeless PFC converter which has the limited bandwidth is connected to the grid. From this, the waveform distortion of the input current is explained and the compensation method for the admittance component is suggested to improve the quality of the input current. Both the simulations and the experiments are performed to verify the analyses taken in this paper for the 1 kW bridgeless PFC converter prototype.

This paper presents the design and control of a high-efficiency multiphase dc-dc converter for a truck auxiliary power unit (APU) fed by a fuel-cell stack. The power-stage design methodology and the operation of the designed power stage used to achieve high efficiency are described in detail. To operate the designed converter as a truck APU, the mode transfer control scheme, where smooth transitions of the voltage and current control modes are necessary, is proposed, and the current controller design procedure is described. A 5-kW four-phase dc-dc converter prototype is built with the proposed power-stage configuration, and the proposed control strategy is applied to control the dc-dc converter. The efficiency of the converter is more than 99.5% at near 10% load and above 98% from 10% to 100% load range. Simulations and experimental results are provided to verify the feasibilities of dc-dc converter operation and the proposed control strategy in the truck APU application.