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This article presents two millimeter-wave frequency reconfigurable dual-band CMOS power amplifiers (PAs) for fifth-generation (5G) communications comprising a single-stage dual-band PA and a two-stage dual-band PA for higher gain. The PAs cover multiple 5G communication bands, n257 (26.5-29.5 GHz) and n260 (37-40 GHz), which use reconfigurable transmission line transformers (TLTs) for output, input, and interstage matching networks. These matching networks allow the operating frequency bands to be changed, thereby achieving optimum performance. The integrated mode selection switches in the transformers reconfigure the inductances of the TLTs to cover two frequency bands, which allows the PAs to have small overall chip sizes. These are fabricated in a 28-nm bulk CMOS process. The single-stage dual-band PA achieves 20.2-/19.1-dBm saturated output power ( ${P}_{sat}$ ), 18.7-/18.6-dBm 1-dB compressed output power ( ${P}_{1 dB}$ ), and 33.6%/32% peak power-added efficiency (PAE) at 26.5 and 37 GHz, respectively, while occupying a chip area of 0.11 mm². The two-stage dual-band PA achieves 19.1-/19.5-dBm ${P}_{sat}$ , 17-/17.8-dBm ${P}_{1 dB}$ , and 31.3%/30.5% PAE at 26.5 and 37 GHz, respectively, while occupying a chip area of 0.165 mm². Both PAs are tested under 64-quadrature amplitude modulation signals with a 100-MHz channel bandwidth. The single-stage PA achieves 14.7- and 12.3-dBm average output powers ( ${P}_{avg}$ ) with -25.1- and -25-dB error vector magnitudes (EVMs) at 26.5 and 37 GHz, respectively. The two-stage PA achieves 12.3- and 11.6-dBm ${P}_{avg}$ 's with -25.3- and -25.1-dB EVMs at 26.5 and 37 GHz, respectively.

A differential four-way power divider for 24 to 30 GHz and a frequency reconfigurable differential four-way power divider for 24 to 30 GHz and 37 to 43.5 GHz are presented. The differential structure provides sound virtual grounds in a multiple-channel chip. Both circuits have a four-way Wilkinson power divider (WPD) configuration based on lumped elements that provide small chip sizes. The first one has a small core chip area of 0.09 mm², a small insertion loss of 0.93 to 1.94 dB, and the port-to-port isolation of 19.1 to 25.6 dB from 24 to 30 GHz. It has a small amplitude and phase differences at four outputs. The second one allows frequency-reconfigurable operation by switching inductances and capacitances to cover widely separated frequency bands (5G NR n257-n261 bands). In addition, switched capacitors (SCs) are inserted to resonate out the parasitic series inductances in isolation resistors at both bands of 24-30 GHz and 37-43.5 GHz. It has a core chip area of 0.168 mm², insertion losses of 1.65-1.89 dB at 24 to 30 GHz and 2.04-2.70 dB at 37 to 43.5 GHz, respectively. The port-to-port isolations are 23.4-37.6 dB at 24 to 30 GHz and 22.6-28.4 dB at 37 to 43.5 GHz.

This article proposes a method to detect vocal signals and the corresponding locations of multiple humans using a multiple-input and multiple-output (MIMO) frequency-modulated continuous-wave (FMCW) radar system. The signals of multiple humans are extracted with digital beamforming by the virtual array generated by MIMO radar processing. To remove body motion artifacts that distort the speech information detected by the radar, a body motion effect cancellation method is proposed. The technique allows recovering vocal signals from detected distorted signals by estimating phase variations due to body motions. A combination of the proposed vocal signal detection algorithm with a human localization one enables to detect speaking humans by means of the MIMO radar. Experiments verify that the proposed method can accurately locate and detect speaking humans based on their vocal vibration signals.

A Ka -band CMOS two-stage Doherty power amplifier (DPA) is presented, whose back-off efficiency is improved by voltage-mode Doherty load modulation. The input and output networks of its power stage are composed of transmission line transformers (TLTs) and single-ended Doherty networks implemented with lumped elements. An adaptive bias circuit to boost the Doherty operation is included in the gate network of the auxiliary amplifier. It shows a power gain of 16.2 dB with 48.2% peak drain efficiency (DE) and 25% 6-dB back-off DE at 26 GHz. It has two times higher 6-dB back-off efficiency in comparison to that of a theoretical class-A power amplifier. It is fabricated in a 28-nm bulk CMOS process and occupies 0.094-mm2 core size.

A 28-GHz linear CMOS cascode power amplifier (PA) that adopts two types of analog linearization methods, dynamic conductance control (DCC) and body carrier injection (BCI), is presented here. The former method controls the load conductance of a common-source (CS) amplifier according to the input power of the PA. This improves the AM–AM and AM–PM characteristics of the cascode PA, which is also analyzed with an equivalent circuit model. The latter injects the carrier signal into the body of a common-gate (CG) transistor, which increases the voltage headroom of the CS transistor. This improves the AM–AM of the cascode PA and also helps to stabilize the PA by reducing the drain–source capacitance of the CG transistor. The proposed PA is fabricated in a 65-nm CMOS process and shows a gain of 15.9 dB, an output 1-dB compression point of 17.7 dBm, and a saturation output power of 19.1 dBm with a peak power-added efficiency (PAE) of 41.2% at 28 GHz.

A method to detect people in multiple locations using a multiple-input and multiple-output (MIMO) frequency-modulated continuous wave (FMCW) radar system is proposed. A 2-D range-angle map is estimated by digital beamforming with virtual receiver arrays obtained via the operation of time-division multiplexing (TDM) MIMO radar. Phase variations due to human vital signs and movements allow the identification of people from stationary clutter in the range-angle map. To improve the sensitivity of phase-based human detection, a curve-length (CL) method that estimates the length of the I/Q signal trajectory is proposed. The proposed method can overcome the codomain limitation of a conventional method through its use of the standard deviation of phase variations. Measurements show that the method improves the signal-to-clutter ratio (SCR) by 10 dB compared with that when using the conventional approach.

An antenna switch embedded in the matching transmission line transformers (TLTs) of a differential power amplifier (PA) and LNA is presented, which selects the transmitter and receiver (Tx and Rx) in 5G communication systems. Because the switching function is implemented in the matching networks of a PA output and an LNA input, the chip size and insertion loss are reduced. A balun, an antenna switch, and matching networks of the PA and LNA are implemented simultaneously by carefully designing a three-port series-combining TLT with Tx and Rx switches. The measured insertion losses of Tx and Rx are 0.42 and 1.01 dB, respectively, at 28 GHz, and the isolation values of the Tx and Rx paths are 24.1 and 31.7 dB, respectively.

A 24-GHz power amplifier (PA) for 5G communication is implemented with a 65-nm bulk CMOS process, which adopts analog linearization techniques of dynamic feedback control (DFC) and an adaptive bias control (ADB). The DFC decreases feedbacks and the ADB increases a gate bias of common sources (CSs) with an increase of the input signal power so that the DFC improves gain flatness and peak efficiency, and the ADB increases high power gain, saturation power, and peak efficiency. These analog linearization techniques lower the IMD3 by improving the AM–AM and AM–phase modulation (PM) of the PA. The proposed PA shows a saturation power of 18.7 dBm, a 1-stage PA gain of 15.3 dB, and a peak PAE of 37.2% with the 24.29-GHz continuous wave signal measurement. It also shows a linear power of 12.9 dBm and a linear PAE of 14.8% with a two-tone signal measurement that has a center frequency of 24.49 GHz and a bandwidth of 80 MHz.

A single-pole double-throw (SPDT) CMOS switch at 15–25 GHz is presented, which has a small size, low insertion losses, and high-power handling capabilities for both output nodes. It has an SPDT structure in which nMOS and pMOS are alternately used as series and shunt transistors. An inductor-matching network is placed between two output nodes for input and output matching, which is also used to increase isolation by resonating out the off capacitances. The proposed SPDT switch is fabricated using a 28-nm CMOS process. It achieves an insertion loss of less than 1.9 dB from 15 to 25 GHz. The measured IP0.2dB of two outputs is 17.4 and 18.3 dBm, respectively. It has an isolation of 25 dB at 20 GHz. The measured ON/OFF switching time is less than 2.3 ns. The proposed SPDT switch has a core area of only 0.02 mm2.

A phase-extraction technique with multiple frequencies of a frequency-modulated continuous-wave (FMCW) radar is proposed, which allows the detection of target motions exactly. An FMCW chirp signal is decomposed into multiple-frequency continuous-wave (CW) signals to extract modulated phases due to target motions. The demodulated phases at multiple frequencies are summed and averaged. Since the proposed method can extract the phase without performing a fast Fourier transform (FFT), it can overcome the range migration problem, which causes an error in phase extraction using a conventional FFT-based method. Therefore, the proposed method can reduce spurious noises induced by phase errors compared with the conventional method. This was verified experimentally for both human vital sign detection and body motion tracking.

A 28-GHz two-stage differential cascode power amplifier (PA) linearized with a simple common-source (CS) body network, in which the body of the CS amplifier at the power stage is connected to the drain through a large resistance. The body network is very simple but very effective to linearize the PA. The linearity improvements are explained and shown with the intermodulation distortions (IMD3) and AM-PM characteristics. The PA also shows a wideband gain because the matching networks consist mainly of transmission-line transformers (TLTs) and distributive interstage matching. It has a gain of 20.1 dB with a bandwidth of 10.8 GHz, a saturation output power of 20.25 dBm, and an output 1-dB compression point of 18.3 dBm, which is fabricated in a 40-nm bulk CMOS process with the area of 0.214 mm 2 .

A 28-GHz in-band full-duplex (IBFD) power amplifier (PA) is presented which integrates a PA with an impedance matched hybrid transformer in a 28-nm bulk CMOS process. The hybrid transformer has a 1:2 turn ratio to match from the optimum load impedance of $25~\Omega $ for a PA to the antenna and balance ports of $100~\Omega $ . Since this allows the additional matching circuits of a PA and an antenna to be obviated, the full-duplex loss is reduced. It shows 28.4-dB isolation between the PA and LNA ports at 28 GHz. For comparisons, a 50- $\Omega $ matched PA and an IBFD PA are designed. The IBFD PA has core sizes of $0.24\times 0.43\,\,{\text {m}}{\text {m}}^{2}$ . Since the impedance matched hybrid transformer has the similar size to the output matching network of the 50- $\Omega $ matched PA, a full duplexer is integrated into the PA without additional chip area. The IBFD PA has 10.6-dB gain and a drain efficiency of 8.9% at 12.3-dBm P1dB.

A 94-GHz highly efficient frequency octupler ( $\times 8$ ) is presented, which consists of a 47-GHz frequency quadrupler followed by a 94-GHz push–push frequency doubler. To achieve high efficiency, the former adopts the current reusing technique of which transistors are biased to be in the class-C region. In addition, the core transistors and the input-matching network of the latter are optimized simultaneously by using a premade input matching network library, which yields a maximum conversion gain under a given dc power budget. It is implemented with a commercial 65-nm CMOS process, which generates −7.12-dBm output power with 0-dBm input signal, consuming only 1 mW of dc power. It operates in the frequency range from 84 to 98.4 GHz (15.3%) within 3-dB gain variation. The total efficiency ( $P_{\text {OUT}}/(P_{\text {dc}} + P_{\text {IN}})$ ) is 9.69%, which is the highest among those of reported frequency octuplers.

A 60-GHz polar vector modulator with a lookup table (LUT)-based calibration for a variable gain active phase shifter is presented. It consists of an input buffer, an I/Q generator, a vector summing amplifier, and 6-bit phase/gain digital-to-analog converters (DACs). It is very difficult to obtain accurate gain and phase characteristics of a polar vector modulator due to circuit imperfections, such as I/Q imbalance, current mismatches of DACs, and impedance variations over polar vector states. Thus, calibrations are essential to have accurate gain and phase states. This letter introduces an LUT-based calibration method to map possible 213 states (5-bit gain and 8-bit phase) onto targeted polar states, which minimizes gain and phase errors drastically. The proposed phase shifter with a generated LUT shows an rms gain and phase errors of 0.13 dB and 0.8°, respectively, at the center frequency of 60 GHz. In addition, it has an rms gain and phase errors of

This letter presents a three-stage differential power amplifier (PA) with an adaptive built-in linearizer (ABL) that achieves an enhanced AM–AM linearity. Series inductors are introduced at cascode internodes to improve the output matching conditions of the cascode amplifiers and stabilize a high-gain PA operation. Capacitors at the gate in the common-gate amplifiers at the power stage are used to achieve high differential gain by reducing RF coupling at the virtual ground and equalizing the drain-source voltage swings. Broad-side coupled transmission line transformers are used for all matching networks. It has 25.5-dB peak power gain and 12.2-dBm saturation output power at 110 GHz with 3-dB bandwidth of 92.5 and 117 GHz. It has a core chip size of 0.76 mm2 and a peak power-added efficiency (PAE) of 8.5%.

This paper describes Ka-band inductor-shared RF switches and their applications to a 35.2-ps 6-bit true-time-delay (TTD) switched-line (SL) phase shifter (PS). The inductor-shared RF switches share an inductor to match the input and output (I/O) ports of different states, which are realized with a switched inductor for SP ${n}\text{T}$ case and with a shared matching network for DP ${n}\text{T}$ case. The switches are applied to controlling most significant 3 bits of the proposed TTD SL PS. The delay lines and reference lines of the PS are implemented with microstrip lines and inverted microstrip lines in the same space, respectively. The dual-side microstrip lines allow it to have not only a small size but also compensation of the loss difference between the signal lines with different lengths. The least significant 3 bits are implemented with the modified structure of the SL PS, which reduces the size further by replacing a reference line by a series switch. The test chip is fabricated in a 65-nm CMOS process. It operates in the range of 20–30 GHz occupying a 0.18 mm2 core size. Its measured insertion loss and IP1dB are 11 dB and 6.5 dBm at 28 GHz, respectively. The measured gain error and rms delay error are less than 2 dB and 0.7 ps at operation frequencies.

A differential phase Doppler radar sensor with multiple receivers (RXs) to remotely detect human vital signals is proposed, which can reduce common motion artifacts as well as common noises to RXs. This is achieved by differentiating two-phase signals from a pair of collocated RXs. Random motions are decomposed into several kinds of motions with respect to the transmitted beam direction. Six differential phase signals are obtained from the four RX combinations, among which at least one pair can get vital signals with reduced common motion artifacts. A weighted-sum method is proposed to combine six differential signals effectively, which allows vital signals to be clearly detected even with large random body motions. A sensor is implemented with a commercially available 24-GHz radar front-end chip with one transmitter and four RXs to verify the differential phase radar concept. An experiment demonstrates that body motion noises are reduced by over 20 dB with the proposed differential phase radar with multiple RXs.

This paper presents matching condition for detector at THz frequencies, which directly read signals from an integrated antenna. We use direct THz-signal detections with CMOS transistors in non-resonant plasma wave mode, which are embedded in on-chip resonating antennas. The detector detects THz envelope signals directly from the side edges of the on-chip patch antennas. The signal detection mechanism is studied in the view of the impedance conditions of the antenna and the detector. The detectors are implemented with stacked transistors structures to achieve high responsivity. The measured responsivities of the detectors with antenna impedances that were simulated to be 599.7, 912.3, 1565, and 3190.6 Ω agree well with the calculated values. Moreover, the responsivity dependence on the detector impedance is shown with two different input impedances of the detectors. Since CMOS circuit models from foundry are not accurate at frequencies higher than f t , the matching guideline between the antenna and the detector is very useful in designing high responsivity detectors. This study found that a detector has to have a large input impedance conjugately matched to the antenna’s impedance to have high responsivity.

A single-pole double-throw antenna switch integrated with a CMOS power amplifier (PA) and a low-noise amplifier (LNA) by using a three-piece transmission line transformer (TLT) for a frequency-modulated interrupted continuous-wave (FMICW) radar front end is presented. The three-piece TLT consists of a PA output TL, an LNA input TL, and a TL connected to an antenna. Parallel switches and $\lambda$ /4 effective impedance transformers are used to provide high isolation. Due to the effective integration, the chip size and overall insertion loss are reduced significantly. The measured results demonstrate that the proposed switch achieves an insertion loss of 2.2 (2.6) dB with an isolation of 33 (33.4) dB in the antenna-to-LNA input (PA output to antenna) direction. The chip, including the PA, LNA, and switch, for a 79-GHz FMICW radar front end is fabricated in 65-nm CMOS technology, and its size is 0.394 mm2. The PA output power is 10.2 dBm at 79 GHz, and the LNA gain is 15 dB at 79 GHz. FMICW radar waveforms are successfully generated with the switch in this chip. The measured results verify that the proposed device generates an FMICW radar waveform at the switching frequency at 6 kHz.

This letter presents a 28-GHz CMOS linear power amplifier (PA) for 5G beamforming front-end that has dual power modes. The proposed PA consists of parallelly connected cascode cells, which are used to linearize the PA in the high-power mode (HPM). Power modes are implemented by splitting the cascode cells again. To have a low-power mode (LPM), half of the cells are turned off while halving the supply voltage simultaneously. This concurrent change makes it possible to keep the phase of the PA unchanged over two power modes while the dc power consumption is reduced by about half in the LPM. In addition, the good linearity is maintained in the LPM. The PA has gains of 18/14 dB, saturated output powers of 18.5/12.2 dBm, P1dBs of 16.5/10.2 dBm, and peak PAEs of 27.3%/17.8% with a 28-GHz continuous wave (CW) signal. The maximum linear output powers that satisfy EVM $\times100$ -MHz 64-QAM OFDM signal.

A variable-gain low-noise amplifier implemented in a 65-nm CMOS process for a beamforming front-end chip is presented, of which the phase remains constant during gain variations. The phase compensation characteristic is achieved by introducing a shunt PMOS and a parallel resistor at the differential outputs of common-gate (CG) transistors. This allows the gain to be controlled without phase variation by adjustment of the combined gate voltage of the CG transistor and the shunt PMOS at the same time. The proposed device shows a gain of 20.8 dB and a noise figure of 3.71 dB at 31 GHz. It shows a root-mean-square phase error of less than 3° over the gain control range of 10.6 dB at 30–34.5 GHz.

A 17-dB on-/off-ratio modulator operating at 290 GHz that switches resonance frequencies of a transmission line resonator with two varactors is presented for ultrashort-distance communication. The resonance frequency is altered by the control voltage of the varactors. The high on/off ratio can be achieved due to a simple resonance control of a transmission line resonator. High-speed modulation is possible due to a small RC time constant associated with a control voltage node. It is fabricated by using a 65-nm CMOS process with a cutoff frequency of 220 GHz. We demonstrated an insertion loss of 3.49 dB, an on/off ratio of 17 dB, a bandwidth of 28 GHz, and data rates as high as 11.3 Gb/s.

This paper presents a highly linear cascode power amplifier (PA) for 5-GHz 802.11ac (wireless local area network) WLAN applications, which is fabricated with a 0.13- $\mu \text{m}$ standard RF CMOS process. A parallel-cascoded configuration is proposed to cancel out third and fifth intermodulation distortions and third harmonic distortion (HD) due to drain–source current nonlinearity. This also reduces distortions due to drain–source and gate-source nonlinear capacitances at both common source (CS) and common gate (CG) stages. The configuration allows the amplifier linear characteristics to be robust against gate node voltage variations of CG transistors compared to previous multigated transistor linearization methods, because the CG transistors always remain in the saturation region and the nonlinearities of capacitances associated with CG transistors cancel each other under a wide range of output powers. In addition, an active feedback linearizer is applied to improve AM–AM and the power-added efficiency (PAE) at high output powers. At 5.15 GHz, the proposed PA is tested with a 256-quadrature amplitude modulation WLAN 802.11ac signal source without digital predistortions. The output powers satisfying the stringent linearity, a −35-dB error vector magnitude, are 17.8, 17.3, and 15.6 dBm with 11.5%, 10.4%, and 7.5% PAEs at 20, 40, and 80 MHz, respectively.

This paper presents a CMOS transceiver IC for a single-antenna frequency-modulated continuous wave (FMCW) radar. Since transmitter (Tx) leakage is critical in a single antenna radar with CMOS technology, a comprehensive leakage canceling technique is proposed. It is able to cancel all the leakages caused by antenna reflection, asymmetry of a balanced structure, and lossy substrate without additional power or area. Even-order harmonic leakages from the power amplifier (PA) are also reduced by an even-harmonic filter, which is implemented simply by removing the real ground from the symmetrical point of the PA output transformer. Matching networks are simplified by using a modified coupler structure. A low-noise combining amplifier is used to make the combining circuit compact. As a result, the transceiver achieves the output power of −1.6 dBm, the phase noise of −105.44 dBc/Hz at 1MHz offset, the receiver (Rx) gain of 15.3 dB, and the noise figure of 11.6 dB. Tx leakages are canceled so that the isolation between Tx and Rx is 47.3 dB. The chip consumes 74.1 mA from a 1.5-V power supply. Despite the high integration level, the chip area including pads is 1.7 mm $\times $ 0.9 mm. A $ {K}$ -band FMCW radar module with a single antenna is implemented with this chip.

A dynamic feedback linearizer for an RF CMOS power amplifier (PA) is presented, which consists of a negative feedback network and a dynamic feedback control circuit to inject a reshaped envelope signal to the network. The linearizer compensates for the gain compression of the RF CMOS PA in high-power region by reducing the feedback dynamically, and it also reduces the amplitude-to-phase modulation (AM-PM) distortions. The PA including the linearizer was fabricated using a 0.18- $\mu \text{m}$ RF CMOS process, which has an output transmission-line transformer on a printed circuit board. It delivers an output power of 28.1 dBm at 1.7 GHz with power added efficiency of 40.9%, and adjacent channel leakage ratio (ACLR $_{\mathrm {E-UTRA}}$ ) of under −30 dBc for a 10-MHz 16-QAM long-term evolution signal without digital predistortions.

A 79-GHz variable-gain vector-sum phase shifter is presented, which consists of 5-bit digital attenuators in respective I and Q paths. It is designed to represent any vectors in the entire IQ plane by controlling the digital attenuators with low phase variations. Variable-gain function can be achieved intrinsically without additional variable-gain circuits. The proposed phase shifter can maintain low phase error at high input powers. The phase shifter provides a root mean square (RMS) phase error of 6.74° with a phase resolution of 11.25°. The gain dynamic range and resolution are 21 and 3 dB, respectively, with an RMS gain error of 1.89 dB.

A simultaneous measurement method of the thickness and permittivity of a thin and uniform material which is attached onto the top of a sensor structure is presented. The sensor utilizes the fundamental and harmonic frequencies of a microstrip line ring resonator structure. The thickness and permittivity of a material under test are calculated from two simultaneous equations at the fundamental and second-harmonic frequencies. Fitting equations to calculate the peak resonant frequencies with respect to the thickness and permittivity are also derived. The structure is implemented with a microstrip line on the front side of a TLY-5A substrate and coplanar waveguide access lines on the backside. The permittivity and thickness of the test material are successfully measured simultaneously.

A common-gate (CG) transistor in a cascode power amplifier has a large input capacitance variation in the saturation region with respect to the source voltage. This causes large nonlinearity in a CMOS PA that utilizes a cascode configuration. Here, we propose a method to reduce the capacitance variation by introducing a parallel auxiliary transistor that works in both the saturation and depletion regions by applying a bias voltage that is slightly different from the main one. This provides the proposed CMOS PA a gain of 27.8 dB and an output power of 16.7 dBm with a PAE of 14.7% for an 802.11n modulated signal with an EVM of −25 dB. © 2016 Wiley Periodicals, Inc. Microwave Opt Technol Lett 59:125–128, 2017

A fully integrated transformer-based quasi-Doherty power amplifier (DPA) with an adaptive power divider (APD) is presented in this paper. A novel folded combining transformer is designed for power combining, which has smaller insertion loss than a conventional one. An APD adaptively controls the power delivered to carrier and peaking amplifiers by altering the input impedance of the peaking amplifier, which has a variable resonance frequency that changes according to the input power. Most of the power is delivered to the carrier amplifier at low incoming power, and it is divided between the carrier and the peaking amplifiers at high incoming power. With continuous wave signal at 1850 MHz, the quasi-DPA implemented with an SOI CMOS process achieves 39.8% and 44.4% power-added efficiencies (PAEs) at the first and the second peak, respectively. With wideband code division multiple access signal, it has 29.2-dBm average linear output power and a 40.47% PAE with a −33-dBc adjacent channel leakage ratio 1. With long-term evolution (LTE) signal, it delivers 27.2-dBm average linear output power and a 37.7% PAE, satisfying linearity requirements for the LTE.

A 79-GHz adaptive-gain and low-noise ultra-wideband radar receiver RF front-end integrated circuit in 65-nm CMOS is presented in this paper. The receiver consists of an adaptive-gain low-noise amplifier (AGLNA) and a ${ g}_{ m}$ -boosted sub-harmonic mixer (SHM). The proposed AGLNA controls the gain with adaptive biased circuits, which lowers the gain as the received signal power increases to provide wide dynamic range to the radar receiver without any external controls. We analyzed the input impedance of a cascode amplifier with a parallel resonant inductor, which improves the noise figure. The proposed ${ g}_{ m}$ -boosted SHM uses a transformer-based feedback network with NMOS bleeding circuits to provide a high conversion gain. The SHM was designed to use a differential local oscillator (LO) signal to have a simple structure and operate at low LO power. The measured conversion gain range was from 16 to $-{\hbox{7.5 dB}}$ with a received power range from $-{\hbox{45}}$ to $-{\hbox{5 dBm}}$ at 79.5 GHz. The measured noise figure was 10.5 dB and the measured 2LO-to-RF isolation was 70 dB. The chip area is ${\hbox{0.47}}\times {\hbox{1.23}}~{\hbox{mm}}^{2}$ .

A CMOS common-gate (CG) combining power amplifier is introduced, which has a simple load impedance adaptor. The CG stage of a cascode amplifier consists of a main amplifier with a load impedance adapter and an auxiliary amplifier with a phase compensator, which are biased for classes AB and C, respectively. The proposed configuration not only increases the efficiency of the power amplifier (PA) at back-off powers, but also increases the linearity at high output powers by canceling AM–AM and AM–PM nonlinearities of the main amplifier with those of the auxiliary amplifier. A load impedance adaptor can be used to match two different optimum load impedances of the main and auxiliary amplifiers simultaneously. A phase compensator is introduced to match the output phases of both amplifiers. It has a die size of $0.9 \times 1.63$ mm2 operates at 2.484 GHz with a 3.3 V supply, which is implemented with the 0.18- $\mu \text{m}$ CMOS technology. It shows a linear output power of 22.1 dBm with a PAE of 32% for an 802.11 n signal at error vector magnitude (EVMs) of −25 dB, and it also shows apparent efficiency improvements at back-off powers.

This letter proposes a highly efficient CMOS linear power amplifier (PA) with cascode–cascade configuration. The proposed configuration improves AM–PM distortion through a capacitance variation compensation of the input capacitance of a common-gate stage in the main amplifier and a common-source stage of an auxiliary amplifier. In addition, the current consumption in the low-power region is significantly reduced structurally because the auxiliary amplifier is turned off. The PA is implemented in 0.18- $\mu \text{m}$ CMOS process with an output combining network in printed circuit board. It provides an average power of 24.5 dBm with a PAE of 45.6% for a long-term-evolution 10-MHz up-link signal with the ACLRE–UTRA of −30 dBc at 2 GHz.

This paper presents a fully integrated W-band 4-GHz bandwidth (BW) pseudo-noise (PN)-coded pulse compression radar transmitter (TX) in a CMOS technology. The PN-coded pulse compression scheme is adopted to obtain high spectral density and to lower the TX leakage using a 63-bit PN code generator based on linear feedback shift registers. We propose a sub-harmonic pumped pulse former and a pulsed power amplifier for high TX efficiency with the suppression of local oscillator (LO)/2LO leakage. A frequency synthesizer including a frequency divider chain generates a sub-harmonic LO signal, as well as a 5-GHz digital clock. Digital blocks with the PN-code generator are synchronized with the clock signal, which makes all pulses start with the same phase. The proposed TX achieves 14.5-dBm maximum output power with the tuning range of 75–81.5 GHz, and the phase noise is ${-}{\hbox{95.2}}$ dBc/Hz at a 1-MHz offset in the range of LO frequencies. In pulse mode, it generates a 4-GHz BW RF pulse signal, which corresponds to a range resolution of 7.5 cm, and the average dc power dissipation is 160 mW.

A K-band CMOS ultra-wideband (UWB) four-channel radar front-end based on timed-array coherent pulsed oscillators is presented. The trigger-signal delay method of the oscillator array with an additional 1-bit RF phase shifter is proposed to achieve beam-forming with wide angular coverage and high angular resolution. The phase coherency of the K-band UWB signal is achieved by using an asymmetric control of the pulsed oscillator. This allows it to detect the direction of a target as well as the accurate distance using a single antenna per channel. The chip is fabricated with ${\hbox{0.13-}}\mu{\hbox{m}}$ CMOS technology and the chip size is 3.9 mm by 1.7 mm. The output spectrum is centered on 26.0 GHz and satisfies the Federal Communications Commission spectral mask. The system attains the angular resolution of 9 $^{\circ}$ in the range from $-{\hbox{45}}^{\circ}$ to $+{\hbox{45}}^{\circ}$ . Total power consumption is only $\sim {\hbox{68 mW}}$ , mainly used in the receiver and digital blocks.

A K-band dual-mode radar transmitter is implemented with 0.13- $\mu \text {m}$ CMOS technology, which supports both FMCW and UWB radar operations. A dual-functional block is proposed to achieve efficient dual-mode operation without additional paths and switches. It is switched between a pulse former and a differential amplifier for UWB and FMCW modes, respectively. As a result, the transmit signal can become either a linearly frequency-modulated signal or a time-slotted pulse signal according to the selected mode. It showed performance comparable to that of previously reported transmitters despite the fact that it operates in dual modes.

A triple-power-mode digital polar CMOS power amplifier (DPA) with a high dynamic range is presented. The triple-power-mode to enhance the efficiency when operating under back-off power is facilitated by the combination of a switched output transformer to change the load impedance and a reduced duty cycle of the LO input signal of the DPA for additional back-off power. This static power-mode method for the low-power region can be used with a DPA which has a high dynamic range in conjunction with a digitally controlled bias generator. An improvement in the PAE from 14.5% to 28.7% is achieved at a back-off power of 6.5 dB from a peak output power of 21.54 dBm at 1.7 GHz. A digital transmit power control (TPC) range of 68.2 dB for WCDMA is realized without any external components.

A reconfigurable adaptive power cell configuration for a multi-band CMOS power amplifier (PA) is presented, for long-range WLAN applications. The common gate (CG) transistor of a CMOS cascode power cell consists of four differently biased 4-transistor cells to have good linearity, two of which are subsidiary cells and are turned off to cover the higher frequency band. This allows the PA to operate in multi-band properly without any additional switches or paths for multi-band. The chip is fabricated in 40 nm CMOS technology, and its size including the ESD-protected pad is $1.985\times 1.61\ \text{mm}^{2}$ . The measurement results show that the proposed PA achieves the output power of 27.8 (28.2) dBm with the PAE of 52% (53%) at a high (low) frequency band.

This letter presents a transmitter at 254 GHz, which uses both amplitude and frequency changes of a transformer-based VCO output by control voltage. Amplitude modulation is achieved by VCO-Q modulation of the VCO with varactor control voltage $(V_{\text{CONT}})$ . Wide-deviation frequency modulation is also achieved due to its wide tuning range, which improves the amplitude modulation by filtering out a low-amplitude band at a receiver. It is fabricated by a 65 nm CMOS process and demonstrates a high data rate of over 10 Gb/s and a low dc power consumption of 23 mW. The amplitude modulation is improved by 9.7 dB with an implemented receiver.

The miniaturized radar sensor for detecting short distances is realized using a six-port network. The six-port network of the radar sensor consists of passive components and RF power detectors. The power detector obtains a highly accurate DC voltage because DC offsets are cancelled using a dummy structure in the detector. The maximum error of a distance measurement to 3 m is approximately 2% for a single target. Using traveling wave antennas, the distances to two targets with different directions are measured with 6.7% maximum detection error to 1 m. © 2014 Wiley Periodicals, Inc. Microwave Opt Technol Lett 56:2634–2637, 2014

We present a synchronization method and coherent ultra-wideband transceivers for a widely separated multiple-input multiple-output (MIMO) radar. Synchronization is essential for MIMO operation, but a spatially spread radar array is not a good structure for it. A wireless cooperative synchronization method is based on coherency of pulse signals and highly accurate delay estimation and they are implemented through a coherent pulse generator and a fine delay-based receiver. Distance measurements of a radar transceiver (TRX) show that the maximum mean error is 4 mm for the target in a range of 0.2 m-8.0 m. Synchronization measurements of two radar TRXs show that the maximum mean error of the asynchronous time difference is 11 ps for the target in a range of 0.25-8.0 m. 2-D images for multiple targets and fluctuational radar cross sections are achieved with the proposed synchronization method under MIMO operation.

This letter presents a dual-mode multi-band second harmonic controlled SOI LDMOS power amplifier (PA). A mode selection switch is designed to have better power handing capability than a conventional switch, which improves performance in low power mode (LPM). To improve the PA's linearity in high power mode (HPM), second harmonic is controlled with the aid of a path for LPM. The PA, implemented with a 0.13- $\mu$ m SOI LDMOS process, operates in triple bands (band 5, 8, and 20) with dual power modes. It is measured using a 16 QAM long-term evolution (LTE) signal with a 10 MHz bandwidth. At 850 MHz, the results show 27.7 dBm average output power (Pout), 31.4 dB gain, and 31.4% power-added efficiency (PAE) with 4% error-vector magnitude (EVM) in HPM and 10.4 dB gain, 15.5 dBm Pout, and 22.5% PAE with 4% EVM in LPM with the LTE signal.