Search

This work presents a novel process to manufacture advanced Germanium-On-Insulator with integrated Silicon Nitride (GOIN) stripes as light waveguide for Ge photonic devices. Through the integration of GOIN stripes, larger tensile strain could be imposed to the bonded Ge layer which may could be used to tailor the bandgap of Ge material for short wave length infrared application. The successful fabrication of advanced GOIN substrate makes the opportunity for monolithic integration of high-performance Ge-based high mobility transistors with photonic components where silicon nitride is the waveguide with low optical loss.

This article presents a novel method to grow a high-quality compressive-strain Ge epilayer on Si using the selective epitaxial growth (SEG) applying the RPCVD technique. The procedures are composed of a global growth of Ge layer on Si followed by a planarization using CMP as initial process steps. The growth parameters of the Ge layer were carefully optimized and after cycle-annealing treatments, the threading dislocation density (TDD) was reduced to 3 × 107 cm−2. As a result of this process, a tensile strain of 0.25% was induced, whereas the RMS value was as low as 0.81 nm. Later, these substrates were covered by an oxide layer and patterned to create trenches for selective epitaxy growth (SEG) of the Ge layer. In these structures, a type of compressive strain was formed in the SEG Ge top layer. The strain amount was −0.34%, meanwhile, the TDD and RMS surface roughness were 2 × 106 cm−2 and 0.68 nm, respectively. HRXRD and TEM results also verified the existence of compressive strain in selectively grown Ge layer. In contrast to the tensile strained Ge layer (globally grown), enhanced PL intensity by a factor of more than 2 is partially due to the improved material quality. The significantly high PL intensity is attributed to the improved crystalline quality of the selectively grown Ge layer. The change in direct bandgap energy of PL was observed, owing to the compressive strain introduced. Hall measurement shows that a selectively grown Ge layer possesses room temperature hole mobility up to 375 cm2/Vs, which is approximately 3 times larger than that of the Ge (132 cm2/Vs). Our work offers fundamental guidance for the growth of high-quality and compressive strain Ge epilayer on Si for future Ge-based optoelectronics integration applications.

Vertical gate-all-around field-effect transistors (vGAAFETs) are considered as the potential candidates to replace FinFETs for advanced integrated circuit manufacturing technology at/beyond 3-nm technology node. A multilayer (ML) of Si/SiGe/Si is commonly grown and processed to form vertical transistors. In this work, the P-incorporation in Si/SiGe/Si and vertical etching of these MLs followed by selective etching SiGe in lateral direction to form structures for vGAAFET have been studied. Several strategies were proposed for the epitaxy such as hydrogen purging to deplete the access of P atoms on Si surface, and/or inserting a Si or Si0.93Ge0.07 spacers on both sides of P-doped Si layers, and substituting SiH4 by SiH2Cl2 (DCS). Experimental results showed that the segregation and auto-doping could also be relieved by adding 7% Ge to P-doped Si. The structure had good lattice quality and almost had no strain relaxation. The selective etching between P-doped Si (or P-doped Si0.93Ge0.07) and SiGe was also discussed by using wet and dry etching. The performance and selectivity of different etching methods were also compared. This paper provides knowledge of how to deal with the challenges or difficulties of epitaxy and etching of n-type layers in vertical GAAFETs structure.

Stacked SiGe/Si structures are widely used as the units for gate-all-around nanowire transistors (GAA NWTs) which are a promising candidate beyond fin field effective transistors (FinFETs) technologies in near future. These structures deal with a several challenges brought by the shrinking of device dimensions. The preparation of inner spacers is one of the most critical processes for GAA nano-scale transistors. This study focuses on two key processes: inner spacer film conformal deposition and accurate etching. The results show that low pressure chemical vapor deposition (LPCVD) silicon nitride has a good film filling effect, a precise and controllable silicon nitride inner spacer structure is prepared by using an inductively coupled plasma (ICP) tool and a new gas mixtures of CH2F2/CH4/O2/Ar. Silicon nitride inner spacer etch has a high etch selectivity ratio, exceeding 100:1 to Si and more than 30:1 to SiO2. High anisotropy with an excellent vertical/lateral etch ratio exceeding 80:1 is successfully demonstrated. It also provides a solution to the key process challenges of nano-transistors beyond 5 nm node.

High-K gate dielectric HfAlO thin films with different temperature annealing treatment have been deposited on the Si substrate by atomic layer deposition. The electrical properties of Hf-films are analysed by measurement of high-frequency capacitance-voltage ( C - V ) and leakage current density-voltage ( J-V ) characteristics. The electrical measurement results indicate the decrease of equivalent oxide thickness (EOT) due to the great change of microstructure and densification after high temperature annealing and the increase of permittivity. However, the interface state density increases. Moreover, the leakage current increases with the increase of annealing temperature. The HfAlO film annealed at 650°C has the best electrical parameters, such as dielectric constant, EOT and leakage current density determined through capacitance-voltage and current density-voltage measurements were 23.5, 0.84, 6.8 × 10 -7 mA·cm -2 , respectively.

Semiconductor nanowires have great application prospects in field effect transistors and sensors. In this study, the process and challenges of manufacturing vertical SiGe/Si nanowire array by using the conventional lithography and novel dry atomic layer etching technology. The final results demonstrate that vertical nanowires with a diameter less than 20 nm can be obtained. The diameter of nanowires is adjustable with an accuracy error less than 0.3 nm. This technology provides a new way for advanced 3D transistors and sensors.

In this article, we demonstrated novel methods to improve the performance of p-i-n photodetectors (PDs) on a germanium-on-insulator (GOI). For GOI photodetectors with a mesa diameter of 10 μm, the dark current at −1 V is 2.5 nA, which is 2.6-fold lower than that of the Ge PD processed on Si substrates. This improvement in dark current is due to the careful removal of the defected Ge layer, which is formed with the initial growth of Ge on Si. The bulk leakage current density and surface leakage density of the GOI detector at −1 V are as low as 1.79 mA/cm2 and 0.34 μA/cm, respectively. GOI photodetectors with responsivity of 0.5 and 0.9 A/W at 1550 and 1310 nm wavelength are demonstrated. The optical performance of the GOI photodetector could be remarkably improved by integrating a tetraethylorthosilicate (TEOS) layer on the oxide side due to the better optical confinement and resonant cavity effect. These PDs with high performances and full compatibility with Si CMOS processes are attractive for applications in both telecommunications and monolithic optoelectronics integration on the same chip.

This work presents the growth of high-quality Ge epilayers on Si (001) substrates using a reduced pressure chemical vapor deposition (RPCVD) chamber. Based on the initial nucleation, a low temperature high temperature (LT-HT) two-step approach, we systematically investigate the nucleation time and surface topography, influence of a LT-Ge buffer layer thickness, a HT-Ge growth temperature, layer thickness, and high temperature thermal treatment on the morphological and crystalline quality of the Ge epilayers. It is also a unique study in the initial growth of Ge epitaxy, the start point of the experiments includes Stranski–Krastanov mode in which the Ge wet layer is initially formed and later the growth is developed to form nuclides. Afterwards, a two-dimensional Ge layer is formed from the coalescing of the nuclides. The evolution of the strain from the beginning stage of the growth up to the full Ge layer has been investigated. Material characterization results show that Ge epilayer with 400 nm LT-Ge buffer layer features at least the root mean square (RMS) value and it’s threading dislocation density (TDD) decreases by a factor of 2. In view of the 400 nm LT-Ge buffer layer, the 1000 nm Ge epilayer with HT-Ge growth temperature of 650 °C showed the best material quality, which is conducive to the merging of the crystals into a connected structure eventually forming a continuous and two-dimensional film. After increasing the thickness of Ge layer from 900 nm to 2000 nm, Ge surface roughness decreased first and then increased slowly (the RMS value for 1400 nm Ge layer was 0.81 nm). Finally, a high-temperature annealing process was carried out and high-quality Ge layer was obtained (TDD=2.78 × 107 cm−2). In addition, room temperature strong photoluminescence (PL) peak intensity and narrow full width at half maximum (11 meV) spectra further confirm the high crystalline quality of the Ge layer manufactured by this optimized process. This work highlights the inducing, increasing, and relaxing of the strain in the Ge buffer and the signature of the defect formation.

In this study, the thermal stability of a Si0.7Ge0.3/Si stacked multilayer for gate-all-around (GAA) MOSFETS is systematically investigated. Rapid thermal annealing (RTA) treatments at temperatures ranging from 800 °C to 1050 °C are performed on the Si0.7Ge0.3/Si stacked multilayer samples. Compared with the as-grown sample, the RTA-treated (800 °C–900 °C) Si0.7Ge0.3/Si stacked multilayer samples attain good crystal quality, a sharp interface between Si0.7Ge0.3 and Si, and minor diffusion of Ge. Furthermore, owing to the rapid diffusion of Ge, the thickness of Si0.7Ge0.3 increases by ∼6 nm and the Ge concentration of Si0.7Ge0.3 reduces by ∼3% as the annealing temperature increases to 950 °C. The interfaces of the Si0.7Ge0.3/Si stacked multilayer disappear and finally behave like a homogeneous SiGe alloy as the annealing temperature further increases to 1000 °C or 1050 °C. Therefore, for thermal stability, the highest tolerable temperature of 900 °C is proposed for the Si0.7Ge0.3/Si stacked multilayer for the fabrication of the GAA device.

Properties of materials are rather interesting under pressure, and much attention has been paid to structural transition induced by pressure. Here the high-pressure behavior of CF 4 has been investigated between 0 and 150 GPa using the first-principles methods. Two structures with C 2/ c and P 2 1 / c symmetries are stable at 0–4.8 and 4.8–22.1 GPa. The lattice parameters agree with the experimental results. Besides, another low-enthalpy structure with space group I 4 ¯ 2 m is favored above 108.3 GPa. Phonon calculations also confirm its dynamical stability. This new high pressure phase of CF 4 may therefore stimulate the experimental work. The electronic structures indicate that CF 4 is a molecular solid under very high pressure.