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International audience; The polyhedral model is a high-level intermediate representation for loop nests that supports elegantly a great many loop optimizations. In a compiler, after polyhedral loop optimizations have been performed, it is necessary and difficult to regenerate sequential or parallel loop nests before continuing compilation. This paper reports on the formalization and proof of semantic preservation of such a code generator that produces sequential code from a polyhedral representation. The formalization and proofs are mechanized using the Coq proof assistant.

The similarity metric in Loop closure detection (LCD) is still considered in an old fashioned way, i.e. to pre-define a fixed distance function, leading to a limited performance. This paper proposes a general framework named LRN-LCD, i.e. a Lightweight relation network for LCD, which combines the feature extraction module and similarity metric module into a simple and lightweight network. The LRN-LCD, an end-to-end framework, can learn a non-linear deep similarity metric to detect loop closures from different scenes. Moreover, the LRN-LCD supports image sequences as input to speed up the similarity metric in real-time applications. Extensive experiments on several open datasets illustrate that LRN-LCD is more robust to strong condition variations and viewpoint variations than the mainstream methods.

In this paper, we advance a multimodal optimization music mashup creation model for loop recombination at scale. The motivation to pursue such a model is to 1) tackle current scalability limitations in state-of-the-art (brute force) models while enforcing the 2) compatibility, i.e., recombination quality, of audio loops, and 3) a pool of diverse solutions that can accommodate personal user preferences or promote different musical styles. To this end, we adopt the Artificial Immune System (AIS) opt-aiNet algorithm to efficiently compute a population of compatible and diverse mashups from loop recombinations. Optimal mashups result from local minima in a feature space that objectively represents harmonic and rhythmic compatibility. We implemented our model as a prototype application named Mixmash-AIS, and conducted an objective evaluation that tackles three dimensions: loop recombination compatibility, mashups diversity, and computational model efficiency. The conducted evaluation compares the proposed system to a standard genetic algorithm (GA) and a brute force (BF) approach. While the GA stands as the most efficient algorithm, its poor results in terms of compatibility reinforce the primacy of the AIS opt-aiNet in efficiently finding optimal compatible loop mashups. Furthermore, the AIS opt-aiNet showed to promote a diverse mashup population, outperforming both GA or BF approaches.

In the literature, loop fusion is an effective optimization technique which tries to enhance parallelizing compilers’ performance via memory hierarchy management, and all its competing criteria create an NP-hard problem. This paper proposes an evolutionary algorithm that aims to achieve a profitable loop order which maximizes fusion taking into account register size, parallelism and data reuse advancement. Besides, this method preserves prerequisite relations between the loops by encoding each distinct loop sequence as the shortest common supersequence (SCS) of the related dependence graph. Regarding the related optimization methods that only focus on fusion, this set of metrics, an evolutionary algorithm and also the shortest common supersequence problem have not been considered before in this area. Despite all the envisaged complexities, experimental results confirm the accuracy and advantage of the proposed approach. But due to evolutionary methods effect on raising the compilation time, the proposed algorithm is only applicable when this issue is not prominent, in comparison with the quality of the outcome.

RNA three-dimensional (3D) structures are critical for RNA cellular functions. However, structure prediction for large and complex RNAs remains a challenge, which hampers our understanding of RNA structure-function relationship. We here report a new web server, the VfoldLA server (http://rna.physics.missouri.edu/vfoldLA), for the prediction of RNA 3D structures from nucleotide sequences and base-pair information (2D structure). This server is based on the recently developed VfoldLA, a model that classifies the single-stranded loops (junctions) into four different types and according to the loop-helix connections, assembles RNA 3D structures from the loop/junction templates. The VfoldLA web server provides a user-friendly online interface for a fully automated prediction of putative 3D RNA structures using VfoldLA. With a single-RNA or RNA-RNA complex sequence and 2D structure as input, the server generates structure(s) with the JSmol visualization along with a downloadable PDB file. The output result may serve as useful scaffolds for future structure refinement studies.

Data-intensive applications are becoming increasingly popular. However, only a few of them with high volume can afford dedicated hardware acceleration (such as Neural Network Processor, or NPU) or platform-specific software implementation (such as Tensorflow running on GPU). In this paper, we propose a hardware and software transparent framework for the acceleration of general-purpose data-intensive applications. Our framework is based on a key insight that most data-intensive applications spend the vast majority of their execution time on some inner loops with abundant opportunities for Data-Level Parallelism (DLP). In particular, we propose SALAD, a static analyzer for loop acceleration by exploiting DLP in hot loops under the LLVM (LLVM compiler infrastructure) framework. In contrast to traditional DLP exploration techniques, SALAD is both software and architectural transparent, without the need to change either the source code or binary code, and does not need vectorized instruction set architecture (ISA) extensions. Instead, it directly works on the program binary code and generates a profile for DLP opportunities in the binary. This profile will be fed to the hardware accelerator transparently to speed up execution. With the experiments result, we estimate that the DLP information provided by SALAD could result in 3.6x-60.2x speedups on a set of benchmarks, depending on their inherent DLP.

Code completion is one of the main features of modern Integrated Development Environments (IDEs). Its objective is to speed up code writing by predicting the next code token(s) the developer is likely to write. Research in this area has substantially bolstered the predictive performance of these techniques. However, the support to developers is still limited to the prediction of the next few tokens to type. In this work, we take a step further in this direction by presenting a large-scale empirical study aimed at exploring the capabilities of state-of-the-art deep learning (DL) models in supporting code completion at different granularity levels, including single tokens, one or multiple entire statements, up to entire code blocks (e.g., the iterated block of a for loop). To this aim, we train and test several adapted variants of the recently proposed RoBERTa model, and evaluate its predictions from several perspectives, including: (i) metrics usually adopted when assessing DL generative models (i.e., BLEU score and Levenshtein distance); (ii) the percentage of perfect predictions (i.e., the predicted code snippets that match those written by developers); and (iii) the "semantic" equivalence of the generated code as compared to the one written by developers. The achieved results show that BERT models represent a viable solution for code completion, with perfect predictions ranging from ~7%, obtained when asking the model to guess entire blocks, up to ~58%, reached in the simpler scenario of few tokens masked from the same code statement., Comment: Accepted to the 18th International Conference on Mining Software Repositories (MSR 2021)

Forests present one of the most challenging environments for computer vision due to traits, such as complex texture, rapidly changing lighting, and high dynamicity. Loop closure by place recognition is a crucial part of successfully deploying robotic systems to map forests for the purpose of automating conservation. Modern CNN-based place recognition systems like NetVLAD have reported promising results, but the datasets used to train and test them are primarily of urban scenes. In this paper, we investigate how well NetVLAD generalizes to forest environments and find that it out performs state of the art loop closure approaches. Finally, integrating NetVLAD with ORBSLAM2 and evaluating on a novel forest data set, we find that, although suitable locations for loop closure can be identified, the SLAM system is unable to resolve matched places with feature correspondences. We discuss additional considerations to be addressed in future to deal with this challenging problem.

One of the challenges for optimizing compilers is to predict whether applying an optimization will improve its execution speed. Programmers may override the compiler's profitability heuristic using optimization directives such as pragmas in the source code. Machine learning in the form of autotuning can assist users in finding the best optimizations for each platform. In this paper we propose a loop transformation search space that takes the form of a tree, in contrast to previous approaches that usually use vector spaces to represent loop optimization configurations. We implemented a simple autotuner exploring the search space and applied it to a selected set of PolyBench kernels. While the autotuner is capable of representing every possible sequence of loop transformations and their relations, the results motivate the use of better search strategies such as Monte Carlo tree search to find sophisticated loop transformations such as multilevel tiling., LLVM-in-HPC 2020 preprint

Primers carry unique genetic information that allows them to be used as specific probes in various applications in the field of diagnostics and particularly in cancer, where the need for accurate treatment selection is crucial. Rapid and affordable detection of cancer specific targets, such as allele-specific single-nucleotide mutational changes, are of great need to improve treatment efficacy and guide clinical use. Detecting these mutations in isothermal conditions creates the opportunity to develop cost-efficient diagnostic platforms for cancer treatment. In this paper, a novel python script was constructed to develop a simple and personalised software tool that could automate the design of allele-specific primers in isothermal conditions using design parameters, such as free energies and annealing temperatures. The scripts' primers were compared to manually designed probes that were experimentally tested on a variant (ESR1 p.E380Q), commonly present in metastatic breast cancer, showcasing the applicability of the method and the potential for the script to be used as part of an automated software to design allele-specific assays for Lab-on-Chip platforms in cancer diagnostics.

Modern compiler optimization is a complex process that offers no guarantees to deliver the fastest, most efficient target code. For this reason, compilers struggle to produce a stable performance from versions of code that carry out the same computation and only differ in the order of operations. This instability makes compilers much less effective program optimization tools and often forces programmers to carry out a brute force search when tuning for performance. In this paper, we analyze the stability of the compilation process and the performance headroom of three widely used general purpose compilers: GCC, ICC, and Clang. For the study, we extracted over 1,000 for loop nests from well-known benchmarks, libraries, and real applications; then, we applied sequences of source-level loop transformations to these loop nests to create numerous semantically equivalent mutations ; finally, we analyzed the impact of transformations on code quality in terms of locality, dynamic instruction count, and vectorization. Our results show that, by applying source-to-source transformations and searching for the best vectorization setting, the percentage of loops sped up by at least 1.15x is 46.7% for GCC, 35.7% for ICC, and 46.5% for Clang, and on average the potential for performance improvement is estimated to be at least 23.7% for GCC, 18.1% for ICC, and 26.4% for Clang. Our stability analysis shows that, under our experimental setup, the average coefficient of variation of the execution time across all mutations is 18.2% for GCC, 19.5% for ICC, and 16.9% for Clang, and the highest coefficient of variation for a single loop nest reaches 118.9% for GCC, 124.3% for ICC, and 110.5% for Clang. We conclude that the evaluated compilers need further improvements to claim they have stable behavior.

Loops are repetitive control structures in programming languages. They are used extensively in many algorithms. The for-loop and while-loop exist, where the former is repeated a number of times while the latter is repeated until a condition is met. Some have asked if re-arranging loops in certain ways can change a program’s speed to produce machine-independent optimisation. Therefore, this research sought to find out if there is any speed difference in a single loop of computations and a loop with an inner loop of same computations. Greater focus is on inner for-loop. The research used a comparative study method in order to evaluate the primary data obtained from running several tests in four popular programming languages: C, C#, Python and R. The Python implementations were further tested on Ubuntu 16 for comparison with results from Windows 10. Results established that, across all languages, there were more computations performed per unit time with an inner for-loop than no inner loop, meaning, given the same number of computations to perform, a loop with an inner for-loop will finish faster. The inner while-loop didn’t perform so well, though. This study will help developers in making better choices with programming language and style.

To write code, developers stitch together patterns, like API protocols or data structure traversals. Discovering these patterns can identify inconsistencies in code or opportunities to replace these patterns with an API or a language construct. We present coiling , a technique for automatically mining code for semantic idioms: surprisingly probable, semantic patterns. We specialize coiling for loop idioms, semantic idioms of loops. First, we show that automatically identifiable patterns exist, in great numbers, with a large-scale empirical study of loops over 25MLOC. We find that most loops in this corpus are simple and predictable: 90 percent have fewer than 15LOC and 90 percent have no nesting and very simple control. Encouraged by this result, we then mine loop idioms over a second, buildable corpus. Over this corpus, we show that only 50 loop idioms cover 50 percent of the concrete loops. Our framework opens the door to data-driven tool and language design, discovering opportunities to introduce new API calls and language constructs. Loop idioms show that LINQ would benefit from an Enumerate operator. This can be confirmed by the exitence of a StackOverflow question with 542k views that requests precisely this feature.

Loopedia is a new database at loopedia.org for information on Feynman integrals, intended to provide both bibliographic information as well as results made available by the community. Its bibliometry is complementary to that of SPIRES or arXiv in the sense that it admits searching for integrals by graph-theoretical objects, e.g. its topology., 16 pages, lots of screenshots

Nowadays processors working in personal computers and mobile devices allow for more and more effective parallel computing. Developers have at their disposal many different methods of implementing concurrency, but usually use the one, that they now best. It is beneficial to know, when a particular technique is good and when it is better to find an alternative. This paper presents different ways of implementing parallel mathematical calculations using threads, tasks, thread pool, task pool and parallel for loop. Each method was used in a C# application running on Windows Presentation Foundation engine on .NET platform. Implemented operation is calculation value of Pi using Leibnitz’s formula.

This paper presents a detailed analysis of the application of Hardware Transactional Memory (HTM) support for loop parallelization with Thread-Level Speculation (TLS) and describes a careful evaluation of the implementation of TLS on the HTM extensions available in such machines. The sample implementation of TLS over HTM described in this paper also provides evidence that the programming effort to implement TLS over HTM support is non-trivial. Thus the paper also describes an extension to OpenMP that both makes TLS more accessible to OpenMP programmers and allows for the easy tuning of TLS parameters. As a result, it provides evidence to support several important claims about the performance of TLS over HTM in the Intel Core and the IBM POWER8 architectures. Experimental results reveal that by implementing TLS on top of HTM, speed-ups of up to 3.8 $\times$ can be obtained for some loops.

Data flow in business process modeling is created and distributed by the exchange of data moving from one task to another in information systems. Among open issues in workflow modeling is the detection of errors in data flow and control flow. Researchers have recently focused on detecting errors by applying an active help with a concept of Data-Record. However, this method does not support a loop modeling. This chapter presents a novel active help with a Data-Record concept in order to detect data flow anomalies in loop modeling. We the improve the active help approach using suitable rules for loop modeling where a decision node, using a data connection as an input data, replaces the connector Xor-split. The input data of the decision node is returned to the last activity as a feedback when the error message is found. The proposed approach is validated using a deterministic finite state process model which uses a logic Boolean predicate (Yes or No) to specify the routing of an input data. In this chapter, anomalies such as missing data, conflicting data and redundant data are investigated. The verification is triggered when an anomaly is detected, and the system is locked until a correction is performed. The results show that Missing Data anomalies are efficiently handled by the proposed approach when there is a feedback loop. The simulation is carried out using The Drools platform which introduced RuleFlow tool in KIE (Knowledge Is Everything). For the other anomalies, conflicting data and redundant data are also verified by a uppaal tool in model checking.

The chapter introduces the concepts of counted ( for ) and conditional ( while ) loops. Many common uses such as summing and counting are covered using the programming method. Nested loops are also introduced. Some more sophisticated uses of loops such as error-checking and combining loops and selection statements are also covered. Finally, vectorizing code, by using built-in functions and operators on vectors and matrices instead of looping through them, is demonstrated. Tips for writing efficient code are emphasized, and tools for analyzing code are introduced.

Development of the manufacturing sector has sparked a wide interest in the study of facility layout problem since the past century. The traditional methods of solving facility layout planning are mainly numerical- and analytical-based simulation which might not reveal the actual situation of a manufacturing system. This paper proposed an interactive solution approach using virtual reality technology for loop layout planning to reduce the gap between numerical results and the real situation through enhanced human-machine interface. In this proposed approach, a virtual loop layout model has been developed as an intuitive and interactive platform for loop layout planning and evaluation in real-time control. This platform allows the user to modify the layout through direct interaction and evaluate the performance of the designed layout for multiple times to obtain the optimal layout design. A case study with the allocation of a shortcut conveyor in a loop layout in different locations conducted within the virtual platform has proven that this platform is an effective alternative solution tool for loop layout decision. The case study shows that the allocation of shortcut conveyor can improve the loop layout performance as it can reduce the traffic congestion of a part and reduce its travel distance by 18.77 %.

Successful application of approximate computing requires cooperation across the entire hardware–software stack. Generally, the hardware will need to provide some means of approximation. If so, it has to be reflected in the instruction set architecture and exposed to assembly programmers or the compiler. At the other end of the stack, users are often required to indicate the amount of accuracy or quality of service loss that is tolerable. The challenge would be to bring the two together in a synergistic and automated workflow so as to maximize the productivity of the developers. This is where the compiler, middleware, runtime, and automated software analysis come into the picture. In this chapter, we shall examine techniques for loop perforation, precision analysis, as well as how to utilize half precision, inexact hardware, and approximate memory with the aim of achieving more energy efficient or better performing code at the expense of user-acceptable loss of accuracy in the results. We shall also discuss the limitations of what current techniques can achieve.

High Level Synthesis development flows rely on user-defined directives to optimize the hardware implementation of digital circuits. Nevertheless, the most beneficial directive values are hard to predict, and exhaustive explorations are infeasible even for moderately complex designs. Focusing on the Loop Unrolling directive, we herein address this challenge by proposing a novel Machine Learning methodology, able to jointly forecast the optimal loop unrolling factors for all the loops in a target application. We showcase that our method results in a better prediction score (up to 63%) and a reduced convergence time compared to other state-of-the-art approaches. Our method achieves 90% of the speedup that can be obtained (with a perfect a-priori knowledge of optimal loop unrolling factors) when synthesizing the computational hotspots of each considered benchmark as hardware accelerators.

International audience; Languages for loop transformations have been leveraged for different type of tools and frameworks in different application domains, yet they lack formal semantics. As a step towards formal specification, this works intends to clarify the underlying concepts of such languages using a denotational approach.

Pipelining techniques execute some loops with cross-iteration dependences in parallel, by partitioning the loop body into a sequence of stages such that the data dependences are not violated. Obtaining good performance for all kinds of loops is challenging and current techniques, e.g., PS-DSWP and LBPP, have difficulties handling load-imbalanced loops. Particularly, for loop iterations that differ substantially in execution time, these techniques achieve load-balancing by assigning work to threads using round-robin scheduling. Algorithms that rely on work-stealing e.g., Piper, efficiently handle load-imbalanced loops, but the high overhead of the scheduler implies poor performance for fine-grained loops.In this paper, we present Proteas, a programming model to allow tradeoffs between load-balancing, partitioning, mapping, synchronization, chunking, and scheduling. Proteas provides a set of simple directives to express the different mappings to handle a loop's parallelism. Then, a source-to-source compiler generates parallel code to support experimentation with Proteas. The directives allow us to investigate various tradeoffs and achieve good performance according to PS-DSWP and LBPP. In addition, the directives make a meaningful comparison to Piper possible. We present a performance evaluation on a 32-core system for a set of popular pipelined programs selected from three widely-used benchmark suites. The results show the tradeoffs of the different techniques and their parameters. Moreover, the results show that efficient handling of load-imbalanced fine-grained loops remains the main challenge.

Developers often rely on automatic vectorization to speed up fine-grained data-parallel code. However, for loop nests where the loops are shorter than the processor's SIMD width, automatic vectorization performs poorly. Vectorizers attempt to vectorize a single short loop, using (at best) a fraction of the processor's SIMD capacity. It is not straightforward to vectorize multiple nested loops together because they typically have memory accesses with multiple strides, which conventional methods cannot profitably vectorize.We present a solution in the context of compiling small tensor multiplication. Our compiler vectorizes several inner loops in order to utilize wide vector parallelism. To handle complicated strides, we devise a vectorizable form of loop tiling. The compiler transforms loops to improve memory locality, then caches tiles of data in vector registers. Strided access patterns are transformed into permute instructions.We show that our compiler is able to significantly speed up many small tensor multiplication algorithms. It judges 13.5% of a randomly generated sample of algorithms to be profitable to vectorize. On these, it generates code 1.55x as fast on average as that produced by GCC's state-of-the-art vectorizer, with a maximum speedup of 10x. We discuss potential extensions to vectorize more general algorithms.

Pragmas for loop transformations, such as unrolling, are implemented in most mainstream compilers. They are used by application programmers because of their ease of use compared to directly modifying the source code of the relevant loops. We propose additional pragmas for common loop transformations that go far beyond the transformations today’s compilers provide and should make most source rewriting for the sake of loop optimization unnecessary. To encourage compilers to implement these pragmas, and to avoid a diversity of incompatible syntaxes, we would like to spark a discussion about an inclusion to the OpenMP standard.

Manycore accelerators have the potential to significantly improve performance of scientific applications when offloading computationally intensive program portions to accelerators. Directive-based high-level programming models, such as OpenACC and OpenMP, are used to create applications for accelerators through annotating regions of code meant for offloading. OpenACC is an emerging directive-based programming model for programming accelerators that typically enable inexperienced programmers to achieve portable and productive performance within applications. In this paper, we present our research in developing challenges and solutions when creating an open-source OpenACC compiler in an industrial framework OpenUH as a branch of Open64. We then discuss in detail techniques we developed for loop scheduling reduction operations on general purpose GPUs. The compiler is evaluated with benchmarks from the NAS Parallel Benchmarks suite and self-written micro-benchmarks for reduction operations. This implementation has been designed to serve as a compiler infrastructure for researchers to explore advanced compiler techniques, extend OpenACC to other programming models, and build performance tools used in conjunction with OpenACC programs. Copyright © 2015 John Wiley & Sons, Ltd.

Developing a high quality compiler tool for application-specific instruction-set processors (ASIPs) including DSP for multimedia application is challenging. The specialization in ASIPs often calls for extensions at the high-level languages to allow the designers to exploit the specialized capabilities. This in turn requires the frontend of the compiler to handle the new syntax and carry the intentions of the designers across to the compiler backend implementations. The backend implementations also require extra efforts for optimized uses of the specialize features of ASIPs. Meanwhile, because of the diversity of the application, it is necessary to make full use of the compiler to complete supports and to make up some shortages of ASIP processors, the corresponding library functions are increased to support of certain operations, such as floating point arithmetic that may not be supported in ASIPs. With the development of the embedded parallelism, the advanced ASIP compilers need the support of parallelism for future application. This paper describes the High-performance C Compiler (HCC) and its specific implementation for an industrial ASIP and its family processors. HCC is a C language compiler extended and retargeted from GCC. A compiler extension framework is proposed processing programming syntax extensions of standard ANSI C for the ASIPs. With target-specific implementation, the adding optimized arithmetic functions library and chips definition file (CDF) as well as the header files for corresponding ASIPs, HCC compiler could be enhanced for the processing capabilities of target processors. Finally, this paper describes a new compiler static allocation and scheduling scheme for loop parallelization based on the OpenMP specification to improve the load imbalance. We have conducted analysis and extensive experiments to verify the correctness and effectiveness of the HCC compiler with the presented ideas. The results show that HCC compiler has a stable performance with excellent codes quality and it has been used in market.

Writing correct parallel programs becomes more and more difficult as the complexity and heterogeneity of processors increase. This issue is addressed by parallelising compilers. Various compiler directives can be used to tell these compilers where to parallelise. This paper addresses the correctness of such compiler directives for loop parallelisation. Specifically, we propose a technique based on separation logic to verify whether a loop can be parallelised. Our approach requires each loop iteration to be specified with the locations that are read and written in this iteration. If the specifications are correct, they can be used to draw conclusions about loop (in)dependences. Moreover, they also reveal where synchronisation is needed in the parallelised program. The loop iteration specifications can be verified using permission-based separation logic and seamlessly integrate with functional behaviour specifications. We formally prove the correctness of our approach and we discuss automated tool support for our technique. Additionally, we also discuss how the loop iteration contracts can be compiled into specifications for the code coming out of the parallelising compiler.

The paper shows a speeding up system for cone-beam generation. We proposed a strategy to accelerate the Feld Kamp, Davis and Kress (FDK) calculation utilizing compiler enhancement procedure called a tiling process. The test was the manner by which to improve the use of the cache by strategies for loop blocking. The guideline reason/motivation behind the loop tiling is to wiping out the cache misses as conceivable as possible. The method is portrayed and indicated by what method can be utilized as a part of recreation code, additionally, a precise model is used in the event of comprehension of the reproduction performance on CPU “multi-core” condition. Exploratory outcomes demonstrate that the purposed strategy accomplishing throughput 8.98 projection for each second (PPS). For remaking 5123-voxel volume from 360 5122 Pixel projections. This execution accomplishes 3.37 speedup and 8.9 throughput over than CPU based strategy that remade before utilizing parallelization method.

Although numerous loop optimization techniques have been designed and deployed in commercial compilers in the past, virtually no common experimental infrastructure nor repository exists to help the compiler community evaluate the effectiveness of these techniques. This paper describes a repository, LORE, that maintains a large number of C language for loop nests extracted from popular benchmarks, libraries, and real applications. It also describes the infrastructure that builds and maintains the repository. Each loop nest in the repository has been compiled, transformed, executed, and measured independently. These loops cover a variety of properties that can be used by the compiler community to evaluate loop optimizations using a broad and representative collection of loops. To illustrate the usefulness of the repository, we also present two example applications. One is assessing the capabilities of the auto-vectorization features of three widely used compilers. The other is measuring the performance difference of a compiler across different versions. These applications prove that the repository is valuable for identifying the strengths and weaknesses of a compiler and for quantitatively measuring the evolution of a compiler.

In this work, we present a monitoring system for Self-Organizing Industrial Systems (SOIS). It is based on an anomaly detection approach which evaluates the movement of objects within a factory by putting them together from sub-trajectories. By introducing two metrics — relative user frequency and pathlet occurence per user — the existing method is extended so that not only anomalous trajectories and omitted production stations can be detected, but also loops, shifts in the load distribution and novel valid paths. For this purpose, suitable visualization techniques are presented: For loop detection the pathlet occurence per user is monitored and evaluated using box plots. Shifts in the load distribution and novel valid paths are detected using heat maps. The work-flow of the monitoring system is illustrated based on data which is generated by a simplified simulation model.

Loop closure detection is a crucial module in simultaneous localization and mapping (SLAM), which reduces the accumulative error in building the environment map. Traditional appearance-based methods mostly utilize hand-crafted features, which are designed based on human expertise. Recent advances in deep learning inspire us to investigate its application in loop closure detection. Different from traditional approaches, deep learning methods automatically learn features from raw data and has better adaptability to complex environment changes. In this paper, we perform a comparison and analysis of several popular deep neural networks and traditional methods for loop closure detection. We evaluate their performance on two open datasets in terms of accuracy and processing time. According to the experimental results, we conclude that deep neural network is suitable for loop closure detection.

Summary Transformations for high-performance superscalar, vector, and parallel processors maximize parallelism and memory locality. Often parallelizing compilers apply transformations, such as loop parallelization and loop vectorization, to convert a sequential array-handling program into a parallel program. Validation of such transformations is extremely useful in the prevalent high-performance computing environment. This paper proposes a novel algorithm for construction of the dependence graph of the generated parallel programs. These transformations are validated by checking equivalence of the dependence graphs of the original sequential program and the transformed parallel program using a standard algorithm reported in the literature. The above equivalence checker works even when the above parallelizing transformations are preceded by various enabling transformations except for loop collapsing transformation that changes the dimensions of the arrays. In the present paper, the scope of the equivalence checker has been expanded to handle this special case by informing it of the correspondence between the index spaces of the corresponding of input and output arrays in the sequential and the parallel programs. The proposed methods are implemented and tested against a set of available benchmark programs that are parallelized by the polyhedral auto-parallelizer LooPo and the auto-vectorizer Scout.

Whether the meaning of a procedure is given by its specification or by its implementation has consequences for scalability of analysis, for localization of errors, for loop semantics, for program translation, and even for the halting problem.

This chapter discusses the key important VHDL constructs. VHDL a is hardware description language and consists of many powerful concurrent and sequential constructs. The key concurrent and sequential constructs are used to describe the design functionality to generate intended hardware. These constructs include process, when else, with select, if then else case, signal and variable declarations and assignments. Even this chapter discusses the important constructs like wait, wait on, wait for, wait until, for loop, and while loop. This chapter is useful for RTL design engineers to understand the VHDL coding styles and synthesizable VHDL. This chapter covers the practical illustrations for every construct. The explanation is given for every synthesizable VHDL code with the synthesis results. This can be useful while working in the FPGA as well as ASIC design domains.

Thread-level speculation becomes more attractive for the exploitation of thread-level parallelism from irregular sequential applications. But it is common for speculative threads to fail to reach the expected parallel performance. The reason is that the performance of speculative threads is extremely complicated by the fact that it not only suffers from the imprecision of compiler-directed performance estimation due to ambiguous control and data dependences, but also depends on the underlying hardware configuration and program behaviors. Thus, this paper proposes a statically greedy and dynamically adaptive approach for loop-level speculation to dynamically determine the best loop level at runtime. It relies on the compiler to select and optimize all loop candidates greedily, which are then proceeded on the cost-benefit analysis of different loop nesting levels for the determination of the order of loop speculation. Under the runtime loop execution prediction, we dynamically schedule and update the order of loop speculation, and ensure the best loop level to be always parallelized. Two different policies are also examined to maximize overall performance. Compared with traditional static loop selection techniques, our approach can achieve comparable or better performance.

We propose a data structure obtained by hierarchically pooling Bag-of-Words (BoW) descriptors during a sequence of views that achieves average speedups in large-scale loop closure applications ranging from 2 to 20 times on benchmark datasets. Although simple, the method works as well as sophisticated agglomerative schemes at a fraction of the cost with minimal loss of performance.

Embedded system design involves meeting strict design goals such as performance, area and power consumption. In-order to meet these design goals embedded systems are implemented in programmable processors and application-specific hardware. Hardware/Software partitioning is thus, a critical step in the realization of embedded systems. The initial software description of the application is profiled to identify the critical sections of the software code which consume the largest percentage of execution time. These critical sections are then chosen as ideal candidates to be implemented as application specific hardware. It is reported that 90 percent of the execution time is spent in executing loops in typical embedded systems applications. In this paper we present a non-intrusive, low overhead FPGA based hardware profiler to identify at run-time the different loops and the time taken to execute these loops from the execution of different scenarios of the application software when compiled on the chosen programmable processor.

In the previous chapter, we mentioned that VBA was Excel’s programming language. It turns out that VBA is the programming language for all the Microsoft Office applications. Also VBA is becoming the programming language of other popular applications. Some of the other applications that are using VBA as its programming language are Visio and Business Objects. This is very exciting news for people who automate applications. The main advantage is that a person does not have to constantly learn a new language when he or she deals with a new application. Another important advantage of an application adopting VBA as a programming language is it is a language that uses most of the programming concepts that professional programmers use; therefore, VBA is a powerful language. Now, it is easier for an Excel programmer to do Access VBA programming, Word VBA, or even PowerPoint VBA programming. The finance people would say that there is a return in the investment of time in learning VBA.

A FOR loop is a computing structure that allows a set of calculations to be made repeatedly for each iteration of the loop where the number of iterations is known in advance. A nested loop happens when a loop is inside another loop. In a spreadsheet program like Microsoft Excel, one can program loops in VBA, its programming language. Spreadsheet developers who do not know how to program in VBA usually implement the equivalent of loops with static values (e.g. region codes and product types are typed as constants) or with formulas (e.g. the region code is the previous region code + 1). In this paper, we present similarities and differences between programming loops and spreadsheet formulas loops. We also present a set of formulas that implement nested loops for 1, 2 or 3 nested levels, along with a generalization for deeper nesting levels. We also provide model management formulas to help the spreadsheet developer ensure that his spreadsheet model covers all the iterations.

This chapter introduces Visual Basic for Applications (VBA) by showing how to construct user-defined functions that can be used both on a worksheet and within other VBA modules. The VBA structures IF..ELSE, SELECT CASE, FOR…NEXT, FOR EACH, and DO WHILE/WHEN are explained and demonstrated. Coding an array function—one that returns data to more than one worksheet cell—is explained.

The automatic place recognition problem is one of the key challenges in SLAM approaches for loop closure detection. Most of the appearance-based solutions to this problem share the idea of image feature extraction, memorization, and matching search. The weakness of these solutions is the storage and computational costs which increase drastically with the environment size. In this regard, the major constraints to overcome are the required visual information storage and the complexity of similarity computation. In this paper, a novel formulation is proposed that allows the computation time reduction while no visual information are stored and matched explicitly. The proposed solution relies on the incremental building of a bio-inspired visual memory using a Fuzzy ART network. This network considers the properties discovered in primate brain. The performance evaluation of the proposed method has been conducted using two datasets representing different large scale outdoor environments. The method has been compared with RatSLAM and FAB-MAP approaches and has demonstrated a decreased time and storage costs with broadly comparable precision recall performance.

This paper presents a fully automatic approach to loop parallelization that integrates the use of static and run-time analysis and thus overcomes many known difficulties such as nonlinear and indirect array indexing and complex control flow. Our hybrid analysis framework validates the parallelization transformation by verifying the independence of the loop's memory references. To this end it represents array references using the USR (uniform set representation) language and expresses the independence condition as an equation, S =0, where S is a set expression representing array indexes. Using a language instead of an array-abstraction representation for S results in a smaller number of conservative approximations but exhibits a potentially-high runtime cost. To alleviate this cost we introduce a language translation F from the USR set-expression language to an equally rich language of predicates ( F ( S ) ==> S = 0). Loop parallelization is then validated using a novel logic inference algorithm that factorizes the obtained complex predicates (F( S )) into a sequence of sufficient independence conditions that are evaluated first statically and, when needed, dynamically, in increasing order of their estimated complexities. We evaluate our automated solution on 26 benchmarks from PERFECT-Club and SPEC suites and show that our approach is effective in parallelizing large, complex loops and obtains much better full program speedups than the Intel and IBM Fortran compilers.

The FALC-Loop web server provides an online interface for protein loop modeling by employing an ab initio loop modeling method called FALC (fragment assembly and analytical loop closure). The server may be used to construct loop regions in homology modeling, to refine unreliable loop regions in experimental structures or to model segments of designed sequences. The FALC method is computationally less expensive than typical ab initio methods because the conformational search space is effectively reduced by the use of fragments derived from a structure database. The analytical loop closure algorithm allows efficient search for loop conformations that fit into the protein framework starting from the fragment-assembled structures. The FALC method shows prediction accuracy comparable to other state-of-the-art loop modeling methods. Top-ranked model structures can be visualized on the web server, and an ensemble of loop structures can be downloaded for further analysis. The web server can be freely accessed at http://falc-loop.seoklab.org/.

To preview of the final appearance of tufted carpet, this paper devises a solution to simulate the color appearance of tufted carpet. The simulation adopts color blocks to represent a single loop pile in carpet surface, through resizing color block size to simulate the extrusion between loop piles. The solution starts from traversing the control pattern to get the pile height level information. Base on the current and surrounded loop piles height level to infer the size and start point of color block for current loop pile. According to patterns’ information to generate the color appearance simulation for loop pile tufted carpet. Base on the proposed simulation, devise the frame work and control logic for simulation software, and developed the simulation software with C++. Simulation test is carried out, the result shows the method can effectively generate carpet color appearance simulation for tufted carpet comprising of multicolor yarns.

Comprehending and debugging computer programs are inherently difficult tasks. The current approach to building program execution and debugging environments is to use exclusively visual stimuli on programming languages whose syntax and semantics has often been designed without empirical guidance. We present an alternative: Sodbeans, an open-source integrated development environment designed to output carefully chosen spoken auditory cues to supplement empirically evaluated visual stimuli. Originally designed for the blind, earlier work suggested that Sodbeans may benefit sighted programmers as well. We evaluate Sodbeans in two experiments. First, we report on a formal debugging experiment comparing (1) a visual debugger, (2) an auditory debugger, and (3) a multimedia debugger, which includes both visual and auditory stimuli. The results from this study indicate that while auditory debuggers on their own are significantly less effective for sighted users when compared with visual and multimedia debuggers, multimedia debuggers might benefit sighted programmers under certain circumstances. Specifically, we found that while multimedia debuggers do not provide instant usability, once programmers have some practice, their performance in answering comprehension questions improves. Second, we created and evaluated a pilot survey analyzing individual elements in a custom programming language (called HOP) to garner empirical metrics on their comprehensibility. Results showed that some of the most widely used syntax and semantics choices in commercial programming languages are extraordinarily unintuitive for novices. For example, at an aggregate level, the word for , as in a for loop, was rated reliably worse than repeat by more than 673% by novices. After completing our studies, we implemented the HOP programming language and integrated it into Sodbeans.

In this paper, we present a technique for compact representation of execution sequences in terms of efficient looping constructs. Here, by a looping construct, we mean a compact way of specifying a finite repetition of a set of execution primitives. Such compaction, which can be viewed as a form of hierarchical run-length encoding (RLE), has application in many very large scale integration (VLSI) signal processing contexts, including efficient control generation for Kahn processes on field-programmable gate arrays (FPGAs), and software synthesis for static dataflow models of computation. In this paper, we significantly generalize previous models for loop-based code compaction of digital signal processing (DSP) programs to yield a configurable code compression methodology that exhibits a broad range of achievable tradeoffs. Specifically, we formally develop and apply to DSP hardware and software synthesis a parameterizable loop scheduling approach with compact format, dynamic reconfigurability, and low-overhead decompression

This paper presents significant improvements in both accuracy and computational efficiency of protein side chain and loop predictions using the Protein Local Optimization Program (PLOP). We introduce a novel energy model in which the internal dielectric constant of the protein is allowed to vary as a function of the interacting residues and present a physical rationale for this model. Using this model, we achieve qualitative improvements in the accuracy of side chain predictions with respect to experimental crystal structure and substantially reduce the RMSDs for loop predictions, particularly those predictions involving charged side chains. For the single side chain prediction of lysine, 40% of the errors are eliminated, and the accuracy increases from 62.6% to 76.8%. The errors in glutamate and aspartate predictions are reduced by 19% and 24%, respectively. When applied to a set of 240 loop predictions with 6, 8, 10, and 13 residue of loop length, this new model yields unprecedented accuracies with average backbone root-mean-square deviations of 0.39 A, 0.68 A, 0.80 A, and 1.00 A for 6, 8, 10, and 13 residue loops, respectively. We also describe a series of technical improvements in the PLOP simulation algorithms, which lead to a speedup of a factor of 2-4 in loop predictions.

We demonstrate the performance of a new implicit solvent model on native protein loop prediction from a large set of loop decoys of 4-to 12-residue in length. The physics-based energy function combines a hydrophobic potential of mean force (HPMF) description with a Generalized Born model for polarization of protein charge by the high dielectric solvent, which we combine with AMBER force field for the protein chain. The novelty of our energy function is the stabilizing effect of hydrophobic exposure to aqueous solvent that defines the HPMF hydration physics, which in principle should be an important stabilizing factor for loop conformations of a protein that typically are more solvent exposed. While our results for short loop decoy sets are comparably good to existing energy functions, we find demonstrable superiority for loop lengths of 8~residue and greater, and the quality of our predictions is largely insensitive to the length of the target loop on a filtered set of decoys. Given that the current weakness in loop modeling is the ability to select the most nativelike loop conformers from loop ensembles, this energy function provides a means for greater prediction accuracy in structure prediction of homologous and distantly related proteins, thereby aiding large-scale genomics efforts in comparative modeling. © 2008 American Chemical Society.