1. Improving SIMO-Regulated Digital SoC Energy Efficiencies Through Adaptive Clocking and Concurrent Domain Control
- Author
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Yidong Chen, Arindam Mandal, Nasser A. Kurd, Chi-Hsiang Huang, Xun Sun, Visvesh S. Sathe, and Venkata Rajesh Pamula
- Subjects
CMOS ,Computer science ,System on a chip ,Voltage droop ,Total system power ,Voltage regulator ,Voltage regulation ,Electrical and Electronic Engineering ,Topology ,Energy (signal processing) ,Voltage - Abstract
Single-inductor multiple-output (SIMO) voltage regulators allow multiple voltage domains to share a single inductor, thus representing a domain-scalable approach to energy-efficient integrated voltage regulation (IVR). However, poor transient response and significant supply voltage ( $V_{dd}$ ) ripple in SIMO regulators induce severe voltage margins. This article quantifies the prohibitive energy-efficiency impact of these margins and proposes two techniques to address them: dynamic droop allocation (DDA) through concurrent domain- $V_{dd}$ control and adaptive clocking using the UniCap architecture. We demonstrate the effectiveness of both techniques on an integrated four-domain SIMO system on chip (SoC) in 65-nm CMOS. Measurements indicate that, compared to conventional SIMO implementations, $V_{dd}$ guardband reductions obtained by UniCap (98%) and DDA (40%) reduce total system power draw by 53% and 31% respectively.
- Published
- 2022