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With the aggressive and amazing scaling of the feature size of semiconductors, hotspot detection has become a crucial and challenging problem in the generation of optimized mask design for better printability. Machine learning techniques, especially deep learning, have attained notable success on hotspot detection tasks. However, most existing hotspot detectors suffer from suboptimal performance due to two-stage flow and less efficient representations of layout features. What is more, most works can only solve simple benchmarks with apparent hotspot patterns like ICCAD 2012 Contest benchmarks. In this paper, we firstly develop a new end-to-end hotspot detection flow where layout feature embedding and hotspot detection are jointly performed. An attention mechanism-based deep convolutional neural network is exploited as the backbone to learn embeddings for layout features and classify the hotspots simultaneously. Experimental results demonstrate that our framework achieves accuracy improvement over prior arts with fewer false alarms and faster inference speed on much more challenging benchmarks.

As the circuit feature size continuously shrinks down, hotspot detection has become a more challenging problem in modern DFM flows. Developed deep learning techniques have recently shown their superiorities on hotspot detection tasks. However, existing hotspot detectors can only handle defect detection from one small layout clip each time, thus may be very time-consuming when dealing with a large full-chip layout. In this paper, we develop a new end-to-end framework that can detect multiple hotspots in a large region at a time and promise a better hotspot detection performance. We design a joint auto-encoder and inception module for efficient feature extraction. A two-stage classification and regression framework is designed to detect hotspot with progressive accurate localization, which provides a promising performance improvement. Experimental results show that our framework enables a significant speed improvement over existing methods with higher accuracy and fewer false alarms.

Layout hotspot detection is of great importance in the physical verification flow. Deep neural network models have been applied to hotspot detection and achieved great successes. The layouts can be viewed as binary images. The binarized neural network (BNN) can thus be suitable for the hotspot detection problem. In this article, we propose a new deep learning architecture based on BNNs to speed up the neural networks in hotspot detection. A new binarized residual neural network is carefully designed for hotspot detection. Experimental results on ICCAD 2012 and 2019 benchmarks show that our architecture outperforms previous hotspot detectors in detecting accuracy and has an $8\times $ speedup over the best deep learning-based solution. Since the BNN-based model is quite computationally efficient, a good tradeoff can be achieved between the efficiency and performance of the hotspot detector by applying ensemble learning approaches. Experimental results show that the ensemble models achieve better hotspot detection performance than the original with acceptable speed loss.

Dummy filling is widely applied to significantly improve the planarity of topographic patterns for the chemical mechanical polishing process in VLSI manufactures. The main challenge of dummy filling is balancing multiple objectives, such as fill amounts, planarity, parasitic capacitance, etc. An obvious drawback of traditional rule-based dummy filling methods is pattern densities, instead of post-chemical mechanical polishing (CMP) topographies, being included in optimization objectives. Although the quality of post-CMP topography strongly depends on pattern features of layouts, especially the density uniformity, however, experimental results show that chip surface variations are not exactly the same as density variations. In this article, a unified dummy fill insertion optimization framework is proposed, integrated with the multiple starting points-sequential quadratic programming (MSP-SQP) optimization solver, where all objectives are considered without approximation. Inside this framework, a full-chip CMP simulator is first integrated to evaluate the planarity of the chip surface. By selecting the initial points smartly with heuristic prior knowledge, the proposed method can be effectively accelerated. The effectiveness of the proposed algorithm is verified with the average 25.8% improvement of quality compared with rule-based methods.

Cell primitive-based functional materials that combine the advantages of natural substances and nanotechnology have emerged as attractive therapeutic agents for cancer therapy. Cell primitives are characterized by distinctive biological functions, such as long-term circulation, tumor specific targeting, immune modulation etc. Moreover, synthetic nanomaterials featuring unique physical/chemical properties have been widely used as effective drug delivery vehicles or anticancer agents to treat cancer. The combination of these two kinds of materials will catalyze the generation of innovative biomaterials with multiple functions, high biocompatibility and negligible immunogenicity for precise cancer therapy. In this review, we summarize the most recent advances in the development of cell primitive-based functional materials for cancer therapy. Different cell primitives, including bacteria, phages, cells, cell membranes, and other bioactive substances are introduced with their unique bioactive functions, and strategies in combining with synthetic materials, especially nanoparticulate systems, for the construction of function-enhanced biomaterials are also summarized. Furthermore, foreseeable challenges and future perspectives are also included for the future research direction in this field.

Scanning electron microscope (SEM) metrology is critical in semiconductor manufacturing for patterning process quality assessment and monitoring. Besides feature width and feature-feature space dimension measurements from critical dimension SEM (CDSEM) images, visual inspection of SEM image also offers rich information on the quality of patterning. However, visual inspection alone leaves considerable room of ambiguity regarding patterning quality. To narrow the room of ambiguity and to obtain more statistically quantitative information on patterning quality, SEM-image contours are often extracted to serve such purposes. From contours, important information such as critical dimension and resist sidewall angle at any location can be estimated. Those geometrical information can be used for optical proximity correction (OPC) model verification and lithography hotspot detection, etc. Classical contour extraction algorithms based on local information have insufficient capability in dealing with noisy and low contrast images. To achieve reliable contours from noisy and low contrast images, information beyond local should be made use of as much as possible. In this regard, deep convolutional neural network (DCNN) has proven its great capability, as manifested in various computer vision tasks. Taking the full advantages of this maturing technology, we have designed a DCNN network and applied it to the task of extracting contours from noisy and low contrast SEM images. It turns out that the model is capable of separating the resist top and bottom contours reliably. In addition, the model does not generate false contours, it also can suppress the generation of broken contours when ambiguous area for contour extraction is small and non-detrimental. With advanced image alignment algorithm with sub-pixel accuracy, contours from different exposure fields of same process condition can be superposed to estimate process variation band, furthermore, stochastic effect induced edge placement variation statistics can easily be inferred from the extracted contours.

Discrete Cosine Transform (DCT) is a commonly used building block for image and video compression. In this article, we present a Markov Random Field (MRF)-based design for DCT implementation because MRF logic gates outperform standard non-MRF units by achieving high noise immunity for applications to logic-based computing systems in deep sub-micron condition. Furthermore, it is found that stochastic logic, a low-cost form of number representation, can also efficiently simplify computations. By combining these two techniques, we present an improved DCT hardware circuit. The example eight-point one-dimensional DCT (1D DCT) system is simulated using 65 nm CMOS technology. Simulation results show that the proposed MRF design can achieve 13% higher noise immunity and 47% area saving, compared with the typical stochastic 1D DCT using classical Master-and-Slave architecture. While achieving the same error rate of 0.21, power consumption is reduced by 52%.

In this article, we propose an efficient correlated Bayesian inference (CBI) method to estimate the system-level failure rates for large-scale circuit systems over multiple process corners. The key idea is to encode the correlations of circuit performances among the different corners into the prior distributions of several carefully defined failure events. The hyper-parameters of these distributions can be learned from a few simulation samples via Bayesian inference and, next, the system-level failure rates over different corners can be simultaneously estimated by taking into account these prior distributions. An iteratively constrained inference method is further developed to guarantee the numerical stability of the proposed method and legalize all estimated failure rates. The numerical experiments demonstrate that compared to the state-of-the-art algorithm, the proposed method can achieve around $10\times $ runtime reduction without surrendering any accuracy.

Tunable analog/RF circuit has emerged as a promising technique to address the significant performance uncertainties caused by process variations. To optimize these tunable circuits after fabrication, most existing post-silicon programming methods are developed by using real-valued performance metrics. However, when measuring a performance of interest on silicon, it is often substantially more expensive to obtain a real-valued measurement than a binary testing outcome (i.e., pass or fail). In this article, we propose a Gaussian Process Classification model to capture the binary performance metrics of tunable analog/RF circuits. Based on these models, post-silicon programming is cast into an optimization problem that can be solved by a novel Bayesian optimization algorithm. Moreover, measurement noises are further incorporated into our proposed post-silicon programming to produce a robust circuit. Two circuit examples demonstrate that the proposed approach can efficiently program tunable circuits with binary performance metrics while other conventional methods are not applicable.

Dummy filling is widely applied to significantly improve the planarity of topographic patterns for the chemical mechanical polishing (CMP) process in VLSI manufacturing. This paper proposes a novel model-based dummy filling synthesis framework NeurFill, integrated with multiple starting points-sequential quadratic programming (MSP-SQP) optimization solver. Inside this framework, a full-chip CMP simulator is first migrated to the neural network, achieving $8134 \times$ speedup on gradient calculation by backward propagation. Multi-modal starting points search is further applied in the framework to obtain satisfying filling quality optimums. The experimental results show that the proposed NeurFill outperforms existing rule- and model-based methods.

In the past decade, the sparsity prior of image is investigated and utilized widely as the development of compressed sensing theory. The dictionary learning combined with the convex optimization methods promotes the sparse representation to be one of the state-of-the-art techniques in image processing, such as denoising, super-resolution, deblurring, and inpainting. Empirically, the sparser of image representation, the better of image restoration. In this work, the non-local clustering sparse representation is applied with optimized matching strategies of self-similar patches, which break through the bottleneck of search window (localization) and improve the estimation effect of the sparse coefficient. The experimental results show that the proposed method provides an effective suppression on noise, preserves more details of image and presents more comfortable visual experience.

Knee osteoarthritis (OA) is a chronic disease that considerably reduces patients' life quality. Preventive therapies require early detection and lifetime monitor of OA progression. In the clinical environment, the severity of OA is classified by Kellgren and Lawrence (KL) grading system, ranging from KL-0 to KL-4. Recently, deep learning methods were applied to OA severity assessment to improve the accuracy and efficiency. Researchers fine-tuned convolution neural networks (CNN) on the OA dataset and built end-to-end approaches. However, this task is still challenging due to the ambiguity between adjacent grading, especially in early-stage OA. Low confident samples, which are less representative than the typical ones, undermine the training process. Targeting the uncertainty in the OA dataset, we propose a novel learning scheme that dynamically separates the data into two sets according to their reliability. Besides, we design a hybrid loss function to help CNN learn from the two sets accordingly. With the proposed approach, we emphasize the typical samples and control the impacts of low confident cases. Experiments are conducted in a five-fold manner. Our method achieves a mean accuracy of 70.13\% on the five-class OA assessment task, which outperforms all other start-of-art methods. Despite that early-stage OA detection still benefits from the human intervention of lesion region selection, our approach achieves superior performance on the KL-0 vs. KL-2 task. Moreover, we design an experiment to validate large-scale automatic data refining during training. The result verifies the ability of characterizing low confidence samples by our approach. Dataset used in this paper was obtained from the osteoarthritis Initiative.

Miniaturized radar near-field imaging systems have become a hot spot for SAR imaging in recent years. The irregular synthetic aperture caused by arbitrary motion of miniaturized system is an important factor affecting imaging quality. On the other hand, the design of fast and high resolution 3D imaging methods is also a major issue. In this paper, a fast time-frequency joint three-dimensional imaging algorithm based on aperture linearization is proposed. First, irregular synthetic aperture is adjusted through special linearization method, and then the target is quickly and accurately imaged. Through formula derivation and simulation test analysis, the results show that the proposed method is feasible and maneuverable, which can solve the current problems.

In this paper, we propose an efficient Bayesian optimization approach for analog circuit synthesis based on the multi-task Gaussian process model. Instead of building the Gaussian process models separately for each circuit specification as the traditional Bayesian optimization methods do, we extend the Gaussian process to a vector-valued function with a shared covariance function to learn the dependencies between different specifications of circuits. The weighted expected improvement function is selected as the acquisition function to cope with the constraints. The experimental results show that the proposed method can reduce the number of simulations while achieving better optimization results.

In this paper, a graph-constrained sparse performance modeling method is proposed for analog circuit optimization. It builds sparse polynomial models constrained by an acyclic graph. These models can be used to solve analog optimization problems within local design spaces by using convex semidefinite programming relaxation both efficiently and robustly. Our numerical examples demonstrate that the proposed modeling and optimization method can quickly and accurately converge to a superior solution for analog circuits while the conventional method fails to work.

In this work, instead of designing deeper convolutional neural networks, we investigate the relationship between the nonlinearity of convolution layer and the performance of the network. We modify the normal convolution layer by inserting quadratic convolution units which can map linear features to a higher-dimensional space in a single layer so as to enhance the approximability of the network. A genetic algorithm-based training scheme is adopted to reduce the time and space complexity caused by the quadratic convolution. Our method is experimented on classical image classification architectures including VGG-16 Net and GoogLeNet and outperforms the original models on the ImageNet classification dataset. The experimental results also show that better performance of our method can be achieved with a shallower architecture. We notice that VGG-16 model is widely used in popular object detection frameworks such as faster R-CNN and SSD. We adopt our modified VGG-16 model in these frameworks and also achieve improvements on PASCAL VOC2007 and VOC2012 dataset.

Compressive sensing (CS) is a novel signal processing technology to reconstruct the sparse signal at sub-Nyquist rate. Orthogonal matching pursuit (OMP) is one of the most widely used signal reconstruction algorithms. However, the least square problem (LSP) in OMP algorithm limits its performance. This paper presents a fast CS reconstruction algorithm implemented on field-programmable gate array (FPGA) using OMP. The proposed algorithm adopts an incremental QR decomposition (QRD) method to efficiently solve the LSP. The incremental QRD is further optimized to eliminate the square root operation to facilitate hardware implementation. The proposed architecture avoiding the complex square root unit mainly consists of some more basic computing units, where the computing process is broken down into several simple operations to map to the corresponding hardware for pipelining. The proposed implementation based on Xilinx Kintex-7 FPGA exploits the parallelism by a well-planned workload schedule and reaches an optimal tradeoff between the latency and frequency. The experimental results demonstrate that the proposed architecture can run at a frequency of 210 MHz with a reconstruction time of 238 $\mu \text{s}$ for 36-sparse 1024-length signal, which improves the signal reconstruction speed by $1.43\times $ compared to the state-of-the-art implementations.

Memory bandwidth has become a bottleneck that impedes performance improvement during the parallelism optimization of the datapath. Memory partitioning is a practical approach to reduce bank-level conflicts and increase the bandwidth on a field-programmable gate array. In this work, we propose a memory partitioning approach for multi-pattern data access. First, we propose to combine multiple patterns into a single pattern to reduce the complexity of multi-pattern. Then, we propose to perform data reuse analysis on the combined pattern to find data reuse opportunities and the non-reusable data pattern. Finally, an efficient bank mapping algorithm with low complexity and low overhead is proposed to find the optimal memory partitioning solution. Experimental results demonstrated that compared to the state-of-the-art method, our proposed approach can reduce the number of block RAMS by 58.9% on average, with 79.6% reduction in SLICEs, 85.3% reduction in LUTs, 67.9% in reduction Flip-Flops, 54.6% reduction in DSP48Es, 83.9% reduction in SRLs, 50.0% reduction in storage overhead, 95.0% reduction in execution time, and 77.3% reduction in dynamic power consumption on average. Meanwhile, the performance can be improved by 14.0% on average.

In this paper, a novel radiation-hardened 14-transistor SRAM bitcell with speed and power optimized [radiation-hardened with speed and power optimized (RSP)-14T] for space application is proposed. By circuit- and layout-level optimization design in a 65-nm CMOS technology, the 3-D TCAD mixed-mode simulation results show that the novel structure is provided with increased resilience to single-event upset as well as single-event–multiple-node upsets due to the charge sharing among OFF-transistors. Moreover, the HSPICE simulation results show that the write speed and power consumption of the proposed RSP-14T are improved by ~65% and ~50%, respectively, compared with those of the radiation hardened design (RHD)-12T memory cell.

An effect method based on machine learning is developed for hotspots mining in lithography. A series of models are trained independently and combined to achieve high accuracy. Innovatively, contour information is firstly adopted to assist the hotspot detection, which eases the very challenging task of detection for topology aberration caused by complicated process effects. More importantly, the proposed method based on new methodology provides high efficiency which is competent for high volume manufacturing.

This paper firstly focuses on yield estimation problem on post-layout-simulation of high dimensional SRAM arrays. Post-layout-simulation is much more credible than pre-simulation. However, it introduces strong relationship among SRAM columns. The Multi-Fidelity Gaussian Process model between the small and the large SRAM arrays near Optimal Shift Vector (OSV) is built. An iterative strategy is proposed and Multi-Modal method is applied to obtain more prior knowledge of the small SRAM arrays and further accelerate convergence. Experimental results show that the proposed method can gain 5-7x speedup with less relative errors than the state-of-the-art method for 384D cases.

Bayesian optimization has been successfully introduced to analog circuit synthesis recently. Since the evaluations of performances are computational expensive, batch Bayesian optimization has been proposed to run simulations in parallel. However, circuit simulations may fail during the optimization, due to the improper design variables. In such cases, Bayesian optimization methods may have poor performance. In this paper, we propose a Robust Batch Bayesian Optimization approach (RBBO) for analog circuit synthesis. Local penalization (LP) is used to capture the local repulsion between query points in one batch. The diversity of the query points can thus be guaranteed. The failed points and their neighborhoods can also be excluded by LP. Moreover, we propose an Adaptive Local Penalization (ALP) strategy to adaptively scale the penalized areas to improve the convergence of our proposed RBBO method. The proposed approach is compared with the state-of-the-art algorithms with several practical analog circuits. The experimental results have demonstrated the efficiency and robustness of the proposed method.

In this paper, we propose an efficient parametric yield estimation method based on Bayesian Inference. By observing that nowadays analog and mixed-signal circuit is designed via a multi-stage flow, and that the circuit performance correlation of early stage and late stage is naturally symmetrical, we introduce a general region to capture the common features of the early and late stage. Meanwhile, two private regions are also incorporated to represent the unique features of these two stages respectively. Afterwards, we introduce classifiers one for each region to explicitly encode the correlation information. Next, we set up a graphical model, and consequently adopt Bayesian Inference to calculate the model parameters. Finally, based on the obtained optimal model parameters, we can accurately and efficiently estimate the parametric yield with a simple sampling method. Our numerical experiments demonstrate that compared to the state-of-the-art algorithms, our proposed method can better estimate the yield while significantly reducing the number of circuit simulations.

Bayesian optimization is a promising methodology for analog circuit synthesis. However, the sequential nature of the Bayesian optimization framework significantly limits its ability to fully utilize real-world computational resources. In this paper, we propose an efficient parallelizable Bayesian optimization algorithm via Multi-objective ACquisition function Ensemble (MACE) to further accelerate the optimization procedure. By sampling query points from the Pareto front of the probability of improvement (PI), expected improvement (EI) and lower confidence bound (LCB), we combine the benefits of state-of-the-art acquisition functions to achieve a delicate tradeoff between exploration and exploitation for the unconstrained optimization problem. Based on this batch design, we further adjust the algorithm for the constrained optimization problem. By dividing the optimization procedure into two stages and first focusing on finding an initial feasible point, we manage to gain more information about the valid region and can better avoid sampling around the infeasible area. After achieving the first feasible point, we favor the feasible region by adopting a specially designed penalization term to the acquisition function ensemble. The experimental results quantitatively demonstrate that our proposed algorithm can reduce the overall simulation time by up to 74 times compared to differential evolution (DE) for the unconstrained optimization problem when the batch size is 15. For the constrained optimization problem, our proposed algorithm can speed up the optimization process by up to 15 times compared to the weighted expected improvement based Bayesian optimization (WEIBO) approach, when the batch size is 15., Comment: 14 pages, 5 figures

This paper introduces a real-time processing and classification of raw sensor data using a convolutional neural network (CNN). The established system is a microcontroller-unit (MCU) implementation of an intelligent gripper for shape identification of grasped objects. The pneumatic gripper has two embedded accelerometers to sense acceleration (in the form of vibration signals) on the jaws for identification. The raw data is firstly transferred into images by short-time Fourier transform (STFT), and then the CNN algorithm is adopted to extract features for classifying objects. In addition, the hyperparameters of the CNN are optimized to ensure hardware implementation. Finally, the proposed artificial intelligent model is implemented on a MCU (Renesas RX65N) from raw data to classification. Experimental results and discussions are introduced to show the performance and effectiveness of our proposed approach.

SEM-image contours provide valuable information about patterning quality and capability. Geometrical properties such as critical dimension and resist sidewall angle could be extracted or estimated from SEM image contours. Those geometrical properties can be used for OPC model calibration, OPC model verification and lithography hotspot detection. This work presents a machine learning based method for contour extraction of SEM image. A designed DCNN network and self-made high quality dataset are combined for contour model training. Based on the high capability of image/feature representation and remarkable advantage of parallel computing with hardware acceleration, the model achieves high accuracy and real-time operation for contour extraction, more importantly, it provides the ability to distinguish and separate the top and bottom contours of SEM images. Additionally, the model not only removes the abundant edges but also repairs the local discontinuity caused by imperfect process and measuring technique.

Bayesian Optimization (BO) is an efficient method for black-box optimization problems. It has been successfully applied to the analog circuit sizing problem. However, all the design variables are viewed as continuous variables in these methods. Actually, many design variables are discrete due to the design rules. In this paper, we proposed an improved BO method for analog circuit sizing with both discrete and continuous variables. We also utilize the Gaussian Process (GP) regression model as the surrogate model for BO. However, we modified the kernel of GP and make it applicable to mixed variables. Experimental results demonstrated that the proposed mixed-variable BO method can significantly reduce the number of simulations with comparable optimization results, compared with the existing BO methods.

To efficiently estimate parametric yields over multiple process, voltage, temperature corners for binary output circuits, we propose a novel Bayesian Inference method based on Bernoulli distribution with conjugate prior in this paper. The key idea is to adopt a product of Beta distributions as the conjugate prior for the yields and encode circuit performance correlations among different corners into this prior. Next, the hyper-parameters are optimized by using multi-start Quasi-Newton method, and the yields over different corners are estimated via maximum-a-posteriori. Two circuit examples demonstrate that the proposed method achieves up to 3.0× cost reduction over the state-of-the-art methods without surrendering any accuracy.

Acceleration and wide deployability in deeper recurrent neural network is hindered by high demand for computation and memory storage on devices with memory and latency constraints. In this work, we propose a novel regularization method to learn hardware-friendly sparse structures for deep recurrent neural networks. Considering the consistency of dimension in continuous time units in recurrent neural networks, low-rank structured sparse approximations of the weight matrices are learned through the regularization without dimension distortion. Our method is architecture agnostic and can learn compact models with higher degree of sparsity than the state-of-the-art structured sparsity learning method. The structured sparsity rather than random sparsity also facilitates the hardware implementation. Experiments on language modeling of Penn TreeBank dataset show that our approach can reduce the parameters of stacked recurrent neural network model by over 90% with less than 1% perplexity loss. It is also successfully evaluated on larger highway neural network model with word2vec dataset like enwik8 and text8 using only 20M weights.

This paper presents an efficient memory partitioning algorithm for multi-pattern data access in Spintransfer torque random access memory (STT-RAM). The algorithm generates check patterns to solve read disturbance problem while ensuring multi-pattern data access in parallel. The implementation results imply that our proposed approach highly outperforms state-of-the-art algorithm in terms of bank number, searching time, performance and storage overhead.

Due to time-consuming SPICE simulations and extremely low failure rates, yield optimization for large static random access memory (SRAM) circuits is still a challenging problem. In this paper, a novel robust yield optimization problem is firstly proposed for SRAM circuits, where robust means considering design and process parameter variations simultaneously. Both a multi-fidelity Gaussian process regression model, which utilizes the strong nonlinear relationship between small and large SRAM columns, and a Bayesian optimization framework are applied to guide the sampling of the expensive large SRAM circuits. A multimodal problem is formulated to find all peaks and valleys on the small SRAM circuits. Such precomputational knowledge can accelerate the convergence of the proposed multi-fidelity and Bayesian optimization framework. Experimental results show that robust yield is essential to yield optimization, for traditional optimal design will degenerate with 4-5 orders of magnitude of yields, if design variations considered, and it doesn’t coincide with the new optimum under the robust yield. The proposed method can gain a 3∼4× speedup compared to the state-of-the-art method without loss of accuracy.

In this paper, we propose EasyBO, an Efficient ASYnchronous Batch Bayesian Optimization approach for analog circuit synthesis. In this proposed approach, instead of waiting for the slowest simulations in the batch to finish, we accelerate the optimization procedure by asynchronously issuing the next query points whenever there is an idle worker. We introduce a new acquisition function that can better explore the design space for asynchronous batch Bayesian optimization. A new strategy is proposed to better balance the exploration and exploitation and guarantee the diversity of the query points. And a penalization scheme is proposed to further avoid redundant queries during the asynchronous batch optimization. The efficiency of optimization can thus be further improved. Compared with the state-of-the-art batch Bayesian optimization algorithm, EasyBO achieves up to 7.35 times speed-up without sacrificing the optimization results., Comment: 6 pages, 6 figures

An effective algorithm is designed for incorporating in a 3D stacked CMOS image sensor for image denoising in ultra-low light conditions. The algorithm originates from sparsity-prior of image and non-locally clustered sparse representation. The simulation results of the CIS image signal processing (ISP) demonstrate high-performance at intense noise level of ultra-low light images, which reveal a great potential of the CIS design in various applications such as night shot, security monitoring, machine-state inspection, medical imaging, biophysics detection, etc.

Bayesian optimization with Gaussian Process (GP) models has been proposed for analog synthesis since it is efficient for the optimizations of expensive black-box functions. However, the computational cost for training and prediction of Gaussian process models are O(N3) and O(N2), respectively, where N is the number of data points. The overhead of the Gaussian process modeling would not be negligible as N is relatively large. Recently, a Bayesian optimization approach using neural network has been proposed to address this problem. It reduces the computational cost of training and prediction of Gaussian process models to O(N) and O(1), respectively. However, reducing the infinite-dimensional kernel to finite-dimensional kernel using neural network mapping would weaken the characterization ability of Gaussian process. In this paper, we propose a novel Bayesian optimization approach using Sparse Pseudo-input Gaussian Process (SPGP). The idea is to use M < N so-called inducing points to build a sparse Gaussian process model to approximate the conventional exact Gaussian process model. Without the need to sacrifice the modeling ability of the surrogate model, it also reduces the computational cost of both training and prediction to O(N) and O(1), respectively. Several experiments were provided to demonstrate the efficiency of the proposed approach.

Accurate and rapid defect identification based on pulsed eddy current testing (PECT) plays an important role in the structural integrity and health monitoring (SIHM) of in-service equipment in the renewable energy system. However, in conventional data-driven defect identification methods, the signal feature extraction is time consuming and requires expert experience. To avoid the difficulty of manual feature extraction and overcome the shortcomings of the classic deep convolutional network (DCNN), such as large memory and high computational cost, an intelligent defect recognition pipeline based on the general Warblet transform (GWT) method and optimized two-dimensional (2-D) DCNN is proposed. The GWT method is used to convert the one-dimensional (1-D) PECT signal to a 2D grayscale image used as the input of 2D DCNN. A compound method is proposed to optimize the baseline VGG16, a well-known DCNN, from four aspects including reducing the input size, adding batch normalization layer (BN) after every convolutional layer(Conv) and fully connection layer (FC), simplifying the FCs, and removing unimportant filters in Convs so as to reduce memory and computational costs while improving accuracy. Through a pulsed eddy current testing (PECT) experiment considering interference factors including liftoff and noise, the following conclusion can be obtained. The time-frequency representation (TFR) obtained by the GWT method not only has excellent ability in terms of the transient component analysis but also is less affected by the reduction of image size; the proposed optimized DCNN can accurately identify defect types without manual feature extraction. And compared to the baseline VGG16, the accuracy obtained by the optimized DCNN is improved by 7%, to about 99.58%, and the memory and computational cost are reduced by 98%. Moreover, compared with other well-known DCNNs, such as GoogLeNet, Inception V3, ResNet50, and AlexNet, the optimized network has significant advantages in terms of accuracy and computational cost, too.

As the technology node shrinks to the nanometer scale, process variation become one of the most important issues in IC designs. The industry calls for designs with high yield under process variations. Yield optimization is computationally intensive because traditionally it relies on the Monte-Carlo yield estimation. In this paper, we will first review the Bayesian methods that reduce the computational cost of yield estimation and optimization. By applying Bayes’ theorem, maximizing the circuit yield is transformed to identify the design parameters with maximal probability density, conditioning on the event that the corresponding circuit is “pass”. It can thus avoid repetitive yield estimations during optimization. The computational cost can also be reduced by using the Bayesian optimization strategy. By using the Gaussian process surrogate model and adaptive yield estimation, Bayesian optimization can significantly reduce the number of simulations while achieving even comparable yields for analog and SRAM circuits. We further propose a Bayesian optimization approach for yield optimization via maxvalue entropy search in this paper. The proposed max-value entropy search can better explore the state space, and thus reduce the number of circuit simulations while achieving competitive results.

In this paper, a Bayesian optimization approach is proposed for yield optimization of analog and SRAM circuits. Gaussian process (GP) regression is employed to predict the yield over the design space with uncertainty information. An expected improvement acquisition function is constructed over the model and guides the optimization with a utility-based strategy. These techniques, as a whole, can significantly reduce the number of expensive yield estimations during the optimization procedure. Furthermore, the GP model encodes the observation uncertainties of noise-corrupted objectives, which enables an adaptive control over yield estimations. By ensuring high estimation accuracies for promising designs while tolerating higher variabilities for low-yield ones, the proposed method can significantly cut down the average computational cost of yield estimations without surrendering the accuracy of the final result. Experimental results show that, compared with the state-of-the-art yield optimization approaches, the proposed method can significantly reduce the number of circuit simulations without compromising optimization efficacy.

Drop test is usually adopted in the integrated circuit (IC) testing to estimate the shock resistance capability of IC packaging. Generally, it is very time-consuming for the drop test simulation, and therefore the fast numerical approach is needed to reduce the computational cost. In this paper, we propose an efficient drop test simulator for through-silicon-via (TSV)-based 3-D IC to simulate its mechanical behaviors under drop impact. The proposed simulator is based on the idea of domain decomposition (DD) to improve the condition number of the coefficient matrix of the solver. We further develop two efficient numerical techniques in the simulator to improve its efficiency. First, a second-order formulation is proposed for the initial solution selection in preconditioned conjugate gradient (PCG) solver, which can efficiently reduce the number of PCG iterations at each time point during simulation. Second, an equivalent structure-embedded model is proposed and applied in the first Schwarz iteration to efficiently reduce the number of Schwarz iterations in DD method. Numerical experiments show that the proposed drop test simulator can achieve $7.03\times $ speedup in comparison with the conventional finite-element method-based solver. It is demonstrated in this paper through several examples with multichip layers, of which each chip layer consists of an $8\times 8$ TSV array, that the proposed simulator can be widely applied to reliability analysis of 3-D ICs under drop impact.

Bayesian optimization with Gaussian process as surrogate model has been successfully applied to analog circuit synthesis. In the traditional Gaussian process regression model, the kernel functions are defined explicitly. The computational complexity of training is O(N 3 ), and the computation complexity of prediction is O(N 2 ), where N is the number of training data. Gaussian process model can also be derived from a weight space view, where the original data are mapped to feature space, and the kernel function is defined as the inner product of nonlinear features. In this paper, we propose a Bayesian optimization approach for analog circuit synthesis using neural network. We use deep neural network to extract good feature representations, and then define Gaussian process using the extracted features. Model averaging method is applied to improve the quality of uncertainty prediction. Compared to Gaussian process model with explicitly defined kernel functions, the neural-network-based Gaussian process model can automatically learn a kernel function from data, which makes it possible to provide more accurate predictions and thus accelerate the follow-up optimization procedure. Also, the neural-network-based model has O(N) training time and constant prediction time. The efficiency of the proposed method has been verified by two real-world analog circuits.

This paper presents an efficient multi-fidelity Bayesian optimization approach for analog circuit synthesis. The proposed method can significantly reduce the overall computational cost by fusing the simple but potentially inaccurate low-fidelity model and a few accurate but expensive high-fidelity data. Gaussian Process (GP) models are employed to model the low- and high-fidelity black-box functions separately. The nonlinear map between the low-fidelity model and high-fidelity model is also modelled as a Gaussian process. A fusing GP model which combines the low- and high-fidelity models can thus be built. An acquisition function based on the fusing GP model is used to balance the exploitation and exploration. The fusing GP model is evolved gradually as new data points are selected sequentially by maximizing the acquisition function. Experimental results show that our proposed method reduces up to 65.5\% of the simulation time compared with the state-of-the-art single-fidelity Bayesian optimization method, while exhibiting more stable performance and a more promising practical prospect.

Triple-modular redundancy (TMR), which consists of three identical modules and a voting circuit, is a common architecture for soft-error tolerance. However, the original TMR suffers from two major drawbacks: the large area overhead and the vulnerability of the voter. In order to overcome these drawbacks, we propose a new complementary dual-modular redundancy (CDMR) scheme for mitigating the effect of soft errors. Inspired by the Markov random field (MRF) theory, a two-stage voting system is implemented in CDMR, including a first-stage optimal MRF structure and a second-stage high-performance merging unit. The CDMR scheme can reduce the voting circuit area by 20% while saving the area of one redundant module, achieving at least 26% error-rate reduction at an ultralow supply voltage of 0.25 V with 8.33% faster timing compared to previous voter designs.

Reliability is one of the major concerns for ultralow power circuit designs. Markov random field (MRF) techniques have been applied to logic circuits to resist random noise when operating under ultralow supply voltage or sub-threshold voltage. Although conventional MRF networks can be easily mapped onto simple logic circuits, it becomes difficult when the circuits are large and complex. In this paper, we present a general coding-based partial MRF (CPMRF) method for multi-logic operations in one basic unit, which is referred to as a CPMRF pair. A CPMRF pair saves circuit area by sharing a common MRF network. It also inherits noise immunity from the MRF theory while obtaining noise immunity from the coding structure as a combination of robust “1s” and “0s.” The resulting architectures become more cost effective than conventional ones. To validate the performance of our proof-of-concept design, we fabricated a carry-lookahead adder implemented by the proposed CPMRF pairs using IBM 130-nm CMOS technology. Measurement results indicate that the CPMRF CLA can achieve high noise tolerance with 20% improvement while occupying 37.7% less area and reducing power consumption by 93% compared with the master-and-slave MRF CLA design.

In this paper, we propose an efficient performance trade-off modeling method for analog circuit based on Bayesian Neural Network (BNN). First, we use a single BNN to simultaneously model multiple performances of interest (PoIs) of an analog circuit. This BNN model can be trained by using a novel automatic differential variational inference (ADVI) method with affordable computational cost. Next, the performance trade-off model can be extracted by embedding BNN into Bayesian optimization framework combined with a modified multi-objective evolutionary method. Since the correlations among different PoIs are implicitly encoded in the BNN model, the proposed method can capture the performance trade-off model efficiently and accurately. The numerical experiments demonstrate that compared to the state-of-the-art algorithms, the proposed method can achieve up to 2× runtime reduction without surrendering any accuracy.

Thermomechanical stress is one of the most important issues in performance and reliability analysis of through silicon via-based 3-D integrated circuits (3-D ICs), where an accurate numerical approach is generally needed to produce stress models and identify weak points in the structure. In this paper, we propose a knowledge-oriented nonuniform (KONU) refinement strategy for 3-D IC stress simulation under the framework of a parallel adaptive finite element method (FEM), and apply it in 3-D IC stress and reliability analysis. Parallel adaptive FEM is promising for solving large-scale problems due to its high accuracy and parallel efficiency. It produces refined meshes based on the a posteriori error analysis, which has the quasi-optimal convergence rate for solving the problem. It has high parallel efficiency, which makes it suitable for handling large and complex structures in 3-D ICs. The KONU refinement strategy developed in this paper can efficiently reduce the number of refinement iterations in parallel adaptive FEM for 3-D IC thermomechanical stress simulation and improves the computational efficiency. It is demonstrated in this paper through several examples that parallel adaptive FEM for thermomechanical stress evaluation can be widely applied in 3-D IC reliability analysis, where accurate stress simulation and modeling is exceptionally important to produce accurate results.

The computation-intensive circuit simulation makes the analog circuit sizing challenging for large-scale/complicated analog/RF circuits. A Bayesian optimization approach has been proposed recently for the optimization problems involving the evaluations of black-box functions with high computational cost in either objective functions or constraints. In this paper, we propose a weighted expected improvement-based Bayesian optimization approach for automated analog circuit sizing. Gaussian processes (GP) are used as the online surrogate models for circuit performances. Expected improvement is selected as the acquisition function to balance the exploration and exploitation during the optimization procedure. The expected improvement is weighted by the probability of satisfying the constraints. In this paper, we propose a complete Bayesian optimization framework for the optimization of analog circuits with constraints for the first time. The existing GP model-based optimization methods for analog circuits take the GP models as either offline models or as assistance for the evolutionary algorithms. We also extend the Bayesian optimization algorithm to handle multi-objective optimization problems. Compared with the state-of-the-art approaches listed in this paper, the proposed Bayesian optimization method achieves better optimization results with significantly less number of simulations.

A novel single-arm-worn ECG-based heart disease monitor is proposed in this paper. It is of a potential to provide continuous monitoring of different ECG metrics, and in this study, we focus on the duration of the QRS complex which is the central of an ECG heartbeat. Firstly, to avoid the low wearability induced by traditional chest-ECG or two-wrist ECG, we apply a highly wearable non-standard single-arm-ECG configuration. Afterwards, to estimate the QRS duration from noisy and weak non-standard single-arm-ECG, we propose a new three-stage machine learning framework. It firstly identifies heartbeat locations (R peaks) by a support vector machine classifier, then uses a dynamic time warping approach to locate QRS patterns that are similar to a template learned by a K-medoids clustering method, and finally learns to use the arm-ECG-based QRS duration estimates to predict a standard chest-ECG-based QRS duration trend. Experimental results demonstrate the effectiveness of this novel system, based on data collected from five subjects using our customized hardware prototype and the non-standard signal-arm-ECG configuration. To the best of our knowledge, this is the first study on the a single-arm-worn ECG-based daily heart disease monitor, using advanced signal sensing and machine learning techniques.

Interlayer liquid cooling network has been considered as one of the effective cooling mechanisms for heat dissipation in three dimensional integrated circuits (3D ICs). In this paper, an optimization approach is proposed for 3D IC interlayer cooling network design with consideration of cooling energy minimization and thermal constraints. First, a channel patterning technique is proposed which adopts straight-channel patterns and corner-barrier patterns to efficiently reduce the temperature of hotspots in the chip. Second, an iterative channel pruning process is proposed for cooling network optimization that reduces the temperature gradient and cooling energy. Furthermore, algebraic multigrid-preconditioned generalized conjugate residual solver is applied for thermal simulation in this optimization process to achieve better computational efficiency. Experimental results have shown that the proposed optimization approach can produce optimal interlayer cooling networks with 11.3%–61.3% cooling energy savings and 49.3%–59.4% pumping pressure savings in comparison with the first place winner of 2015 computer-aided design contest at International Conference on Computer-Aided Design.

Yield 1 analysis of SRAM is a challenging issue, because the failure rates of SRAM cells are extremely small. In this article, an efficient non-Gaussian sampling method of cross entropy optimization is proposed for estimating the high sigma SRAM yield. Instead of sampling with the Gaussian distribution in existing methods, a non-Gaussian distribution, i.e., a joint one-dimensional generalized Pareto distribution and ( n -1)-dimensional Gaussian distribution, is taken as the function family of practical distribution, which is proved to be more suitable to fit the ideal distribution in the view of extreme failure event. To minimize the cross entropy between practical and ideal distributions, a sequential quadratic programing solver with multiple starting points strategy is applied for calculating the optimal parameters of practical distributions. Experimental results show that the proposed non-Gaussian sampling is a 2.2--4.1× speedup over the Gaussian sampling, on the whole, it is about a 1.6--2.3× speedup over state-of-the-art methods with low- and high-dimensional cases without loss of accuracy