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As technology evolves into the deep submicron level, synchronous circuit designs based on a single global clock have incurred problems in such areas as timing closure and power consumption. An asynchronous circuit design methodology is one of the strong candidates to solve such problems. To verify the feasibility and efficiency of a largescale asynchronous circuit, we design a fully clockless 32-bit processor. We model the processor using an asynchronous HDL and synthesize it using a tool specialized for asynchronous circuits with a top-down design approach. In this paper, two microarchitectures, basic and enhanced, are explored. The results from a pre-layout simulation utilizing 0.13-μm CMOS technology show that the performance and power consumption of the enhanced microarchitecture are respectively improved by 109% and 30% with respect to the basic architecture. Furthermore, the measured power efficiency is about 238 µW/MHz and is comparable to that of a synchronous counterpart.

InfiniBand technology is being accepted as the future system interconnect to serve as the high-end enterprise fabric for cluster computing. This paper presents the design and implementation of the InfiniBand system interconnect, focusing on an InfiniBand host channel adapter (HCA) based on dual ARM9 processor cores The HCA is an SoC tailed KinCA which connects a host node onto the InfiniBand network both in hardware and in software. Since the ARM9 processor core does not provide necessary features for multiprocessor configuration, novel inter-processor communication and interrupt mechanisms between the two processors were designed and embedded within the KinCA chip. Kinch was fabricated as a 564-pin enhanced BGA (Bail Grid Array) device using 0.18 CMOS technology Mounted on host nodes, it provides 10 Gbps outbound and inbound channels for transmit and receive, respectively, resulting in a high-performance cluster system.

As a fine-grained power gating method for achieving greater power savings, our approach takes advantage of the finite state machine with a datapath (FSMD) characteristic which shows sequential idleness among subcircuits. In an FSMD-based power gating, while only an active subcircuit is expected to be turned on, more subcircuits should be activated due to the power overhead. To reduce the number of missed opportunities for power savings, we deactivated some of the turned-on subcircuits by slowing the FSMD down and predicting its behavior. Our microprocessor experiments showed that the power savings are close to the upper bound.

Due to a half transitions for data transfers comparing with conventional 4-phase signalings, level-encoded dual-rail (LEDR) has been widely used in on-chip asynchronous interconnects supporting a 2-phase handshake protocol. However, it inevitably requires 2N wires for N-bit data transfers to maintain delay-insensitive encoding. Encoder and decoder circuits that perform an asynchronous 2-phase handshake protocol with only N wires for N-bit data transfers are presented for on-chip global interconnects. Their fundamentals are based on a ternary encoding scheme, and the circuits are implemented using current-mode multiple-valued logics. In the simulation with 0.25 μm CMOS technology, the suggested circuits saves both latency and energy consumption over the wire length of 3 mm.

A modified thinning algorithm is proposed and its validity demonstrated. Experimental results show that this modified algorithm preserves the connectivity and the end points, which are critical requirements in a character recognition system. A flexible thinning processor has been integrated and interfaced with an IBM PC AT/386 and been tested for variable image widths from 25 to 40 b. For a 38*38 image and 1.5-kb data, completion of thinning requires 2.8 ms. It is shown that processing speed is limited only to the propagation delays of logic gates, since the input image continuously enters the processor without a control signal. Experimental results confirm that this modified algorithm and processor are effective in image processing as well as character and fingerprint recognition. >

In this paper we propose an algorithm about aggressive, but partial removal of multiplexers used for sharing functional units (FUs). By eliminating some multiplexers and duplicating the FU related, the proposed algorithm could be more advantageous for low power circuits than just keeping the multiplexers. To determine whether a removal of a group of multiplexers is beneficial or not, we compared a FU with multiplexers to multiple replications of the FU without any multiplexer under various conditions. Through the experiments, we aggregated information to be used for finding appropriate multiplexers to be extricated from circuit netlist; using the information, we built an automated algorithm to remove particular multiplexers; we applied it to a netlist of 16 bit processor. The processor that is newly generated by the algorithm consumed average about 12% less power than the initial processor.

A new optimization algorithm of the digital filter over the CSD coefficient is proposed. This method is based on the selective weighting method assigning more number of operations to some coefficients which are more sensitive to the frequency response remaining total number of operations. Also, the optimized coefficient is utilized as Control-RAM and combined with the 4th pipelined AU for the low-power implementation. The designed filter for 24-bit SigmaDelta audio DAC is fabricated with 0.18 um Samsung CMOS technology.

A VLSI processor is designed for the small-scale isolated speech recognition applications. It is a dedicated processor which detects endpoint, extracts LPC (linear predictive coefficient) cepstral coefficients from the speech signal, and computes the spectral distances using a dynamic time warping (DTW) technique. The designed chip can recognize 1000 isolated words per second with an average recognition accuracy of 90.3%. It is designed in a 0.8 /spl mu/m CMOS technology, includes 66,760 gates, and runs with a 10 MHz clock.

An LPC cepstrum processor for speech recognition is implemented on CMOS gate array. The processor that we designed contains a 24 bit floating-point MAC unit, which computes a correlation rapidly, the majority of operations in the algorithm. This processor has 22 register files to store temporary variables, which enable one to reduce access to external memory. For the purpose of fast operations, the floating-point MAC consists of a pipeline structure with 3 stages and uses a branched postnormalization scheme proposed in this paper. Experimental results show that it takes approximately 266 /spl mu/s to process a frame of 20 ms at 15 MHz clock rate. This processor runs at the maximum rate of 16.6 MHz and the number of transistors is 55,520.