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There are numerous examples of biological systems outperforming human-designed algorithms at engineering tasks. Rather than relying on one central controller, these systems rely on distributed agents following simple local interaction rules that yield complex collective behavior. My research studies these biological systems systems in order to reverse-engineer optimization algorithms, with a focus on designing robust, efficient routing networks.Repairing broken links is a fundamental problem for human-designed routing networks, as well as trail networks used by ants to travel between nests and food sources. Many ant species have evolved methods to solve the repair problem under more restrictive constraints than those faced by human engineers. Arboreal turtle ants are especially interesting, because their movements are constrained by the branches in the vegetation. I defined a mathematical model for the unique repair problem faced by turtle ants. I demonstrated techniques for using turtle ant behavioral data to derive a distributed repair algorithm and infer critical features of turtle ant behavior. The algorithm is biologically realistic, scalable, and robust to a variety of topologies. I then analyzed data on trail networks formed by turtle ants over several days to conclude that turtle ant trail networks eschew shorter branches in favor of nodes whose physical orientations allow for quicker pheromone reinforcement. Human-designed routing networks often seek to maximize efficiency while minimizing cost. These objectives often conflict, which necessitates manage trade-offs. Neural arbors face a similar challenge of conducting signals quickly while conserving material. I defined a mathematical framework for the multi-objective optimization problem that neural arbors face. I showed that neural arbors are significantly better at optimizing trade-offs between material cost and signal delay than would be expected by chance. I showed how this framework can be used to predict an arbor's structure based on its function. My work confirms the value of using neural arbors as inspiration for network design algorithms, and identifies promising new avenues for neuroanatomy research.My research highlights the symbiotic relationships between biology and computer science: collecting and analyzing behavioral data can inform algorithm design, while algorithmic thinking can elucidating novel behavioral patterns.

In this work, Prediction of heart attack is very uncontrolled problem faced by doctor abnormally in every hospitals they have to make a killing review feedbacks from their patients. The ability of the sentiment analysis is needful work for machine to get results in the form of feedback i.e. positive or Negative feedback. Machine learning techniques assess necessary job in this area and in this zone of research work to construct a product this can assists the machine learning computations to input the option choice with respect to the fore cast and assess the expectation. Heart disease commonly occurred disease and it is the critical speculation for unexpectedly death these days. Nearest Neighbour (KNN) featureless is the most well-known, viable and productive calculation utilized for acknowledgment. In this paper, evaluate heart disease occurrences prediction by using machine learning strategies. Which will gives comfortable heterogeneous forecast model and it aid to discover best symptomatic for medicinal services framework for early prediction of symptomatic heart disease.

Recently, the latency resulted from the communication between the multi-core processor IP cores and the other IP cores such memory controller and peripherals on the same die SoC became a critical issue especially when all the core processors using advanced interface protocol such AXI4 and make write and read transactions in different burst mode capability. In this paper, we proposed a multi-core memory controller for four core processors using the AXI4 interface protocol. The multi-core memory controller can make the write and read transactions using the AXI4 interface protocol in parallel to improve the entire system speed up on the same die SoC. The SoC design architecture is modeled in System Verilog HDL, simulation and synthesis are done by using the Vivado tool and FPGA ZYNQ-7 ZC702 Evaluation Board (xc7z020clg484-1).

In this paper, presented an efficient 4-level discrete wavelet packet transform (DWPT) using approximation where area and delay are considerably reduced. It gives lesser number of hardware arithmetic computations and lesser delay required at each computation level. Compared with the existing design, the presented design gives 16.34% less area for block size 2. The Area Delay Product (ADP) of proposed shift add register approximated design have saving of 21.7% and CPD of 4.4% lesser for block size 2 over existing design.

The main issue for SoC design in this era is not only which IP cores SoC integrate, but also these IP cores or blocks how they will be interconnected to get high performance data exchange. AXI4 interface protocol is one of the widely SoC interfaces used in several recent designs. In this paper, we designed a memory controller for multi-core processors using the AXI4 interface protocol to improve the performance of the SoC design of the existing work. The multi-core processors represented by JTAG-to-AXI Master IP core and the memory controller represented by AXI BRAM Controller IP core which manages the write and read transactions of multi-core processors while accessing the main memory. Regardless of the type of main memory, Block RAM IP core represents the main memory. Each core processor can access only individual Block RAM which represents the address space of the core processor using the AXI4 interface protocol. The design is successfully implemented on FPGA ZedBoard (xc7z020clg484-l) with a maximum speed frequency of 100 MHz.

The natural scenarios show that the images which are taken under low light environments experiences weak luminosity and low-contrast issues frequently. One of the vital units of image contrast enhancement accelerator is a Histogram computation. In this paper, a new VLSI structure is developed for contrast enhancement using optimized memory-based histogram analysis. Initially, a comparator-less parallel rank ordering filter is proposed to remove the noise in the pre-processing stage. Then, the pipelining and parallel process of the memory-based histogram analysis is enhanced by introducing an enhanced transient search optimization (ETSO) approach that selects suitable data to perform the data comparison process in the processing elements (PEs). In addition, a flexible digital comparators (FDC), pipelined structure of bilinear interpolation and reciprocal units are introduced in the proposed contrast enhancement accelerator to save area and power usage. Also, the histogram memory unit is designed by considering dual data flow with self-configurable characteristics for the selection of appropriate data flow in the contrast enhancement application. At last, the stated VLSI structures for both histogram computation and enhancement unit are implemented in FPGA for meeting their speed and resource constraints. The key factors of the proposed design are lowest delay of 5.256 ns and lower power consumption of 0.289 W against existing accelerators.

Objectives: Stealthy attacks are a kind of attacks which injects route fabrication information and producing false identification in network. In this paper, we evaluate these two stealthy attacks against a privacy mechanism as Distinct Authentication Key Approach (DAKA) in MANET. Methods/Statistical Analysis: Wireless networks are becoming the most popular in today communication systems, where users prefer to have wireless connectivity regardless of its geographic location. However, the openness of wireless communications increases the threat to MANET under its conditions. It is very challenging to validate false identify in a stealthy node behaviour as it gives a normal impression and in case of route fabrication they modify the routing path which leads a high number of packet loss. The DAKA provides a Secure Route Discovery Mechanism and data routing through a privacy and certificate authentication methodology. Findings: We evaluate the proposed approach by measuring Packet Delivery Ratio, Avg. End-to-End Delay, Control Overhead and Packet Drop Ratio with varying the number of malicious nodes in a fixed number of nodes and traffic. Application/ Improvements: The simulation experiment result shows successfully alleviation of the malicious nodes and achieves the needed performance.

Wireless Sensor Networks are considered as basic technique for the social event of data; this will be executed in all organizations, for instance, helpful, opposition, auto-points of view, etc. Remote Sensor Networks generally include group head related to each and every other hub. The assurance of cluster head rule issue, in which the vitality essential, is careful in light of its propensity of social occasion the data’s from neighbouring hubs. The group head needs the careful vitality so it can pass on the whole system information transmission to sink. For handling these issues, a novel calculation is proposed as Dynamic Energy Efficient Mid-point-Based Distance Aware figuring (DEE-M-DA). This is a vitality capable group decision part in the remote sensor arrangement. Basic fundamental is cluster head selection; this depends upon the standard of Midpoint-Residual Energy and Distance (M-RED) structure. K-medoid calculation is utilized to discover the mid-point of the hubs between the sink. This calculation is utilized to compel the division and send the information quickly. Smart information transmission has done among CH and sink. The proposed convention has been recreated utilizing NS-2 test structure and separated other existing conventions.

With the advent of technology, wireless sensor networks (WSNs) are becoming more preferable for diverse applications like in industrial settings for machine monitoring and in large buildings and bridges for structural integrity monitoring. These WSNs comprise different types of sensors based on the application. Each of these sensors transmits their information at different sampling rates to the central gateway (like IOT gateway) in the WSN. In this scenario, to meet the real-time rates, adaptive sampling rate converters (ASRCs) are necessary to the gateway for up/down converting the data collected from different sensors of the network. Therefore, this paper emphasizes the necessity of an efficient ASRC in wireless sensor networks (WSNs), and a case study for an audio is presented using different sampling rate converter structures.

The magnitude of information that is conveyed via the Internet has escalated more rapidly during the last few decades. Image compression provides an appreciable way to dwindle the image size. For the conservation of bandwidth during still image compression, JPEG is advisable. As one can gather and communicate the images early with reduced size, we planned an innovative JPEG compression algorithm (de Queiroz, Member IEEE, IEEE Trans Image Process 7(12):1661−1672, 1998, [1] Prakash, IEEE Member, Mitchell, IEEE Fellow, Stepneski, IEEE Int Conf Image Process 3:494−497, 2001, [2], Sreelekha, Sathidevi, An improved JPEG compression scheme using human visual system model, 2007, [3]) with fuzzy c-means-based clustering in this work. The anticipated algorithm produces enhanced results in comparison with standard algorithms in the form of some estimation parameters like MSE, PSNR, and quantity of bits transmitted (Egger, Li, IEEE Int Conf Image Process 3:326−330, 1994, [4]). The speed is increased with the proposed JPEG algorithm, thereby diminishing the memory that is necessary for hoarding the encoded bits. The reassembled image after decompression is as similar as the image which was sent as an input.

A flexible object recognition system is considered which can compute the good features for high classification of objects. To characterize an output class or object usage of appropriate features is vital for all classification problems. Moment invariant functions are very useful for object classification, regardless of its orientation, size and position. The main features leading us to our objective are representations of objects using 2D images. The proposed paper focus on, the classification performance of classifiers with moment–based feature sets is introduced after only efficient feature extraction. The experimental results shows that the proposed feature descriptor performs well with existing texture descriptors in terms of classification accuracy.

This paper discusses a standard flow on how an automated test bench environment which is randomized with constraints can verify a SOC efficiently for its functionality and coverage. Today, in the time of multimillion gate ASICs, reusable intellectual property (IP), and system-on-a-chip (SoC) designs, verification consumes about 70 % of the design effort. Automation means a machine completes a task autonomously, quicker and with predictable results. Automation requires standard processes with well-defined inputs and outputs. By using this efficient methodology it is possible to provide a general purpose automation solution for verification, given today’s technology. Tools automating various portions of the verification process are being introduced. Here, we have Communication based SOC The content of the paper discusses about the methodology used to verify such a SOC-based environment. Cadence Efficient Verification Methodology libraries are explored for the solution of this problem. We can take this as a state of art approach in verifying SOC environments. The goal of this paper is to emphasize the unique testbench for different SOC using Efficient Verification Constructs implemented in system verilog for SOC verification.

The object face liveness detection for genuine face recognition and user authentication is a difficult task and day to day it becoming an interesting tricky in real time vision and security applications. Since many decades, various authors have proposed new technique and methods and developed but still the system has to improve to recognise the genuine object faces from spoofing objects with increasing in accuracy. However, in account of existing methods were fails in finding of genuine objects from sample objects and individual differences between them. The ordinary classifier cannot simplifies well to various kind of objects in different directions especially in case of blur images. In order to overcome his problem, we proposed an object-specific face authentication system for liveness detection using combined feature descriptors with fuzzy-based SVM classifier, allows to select specific area from whole object, extract features from specific area of object leads reduction in processing time and complexity in feature extraction. Later the system recognise respective faces, finally it checks for live objects with the help of fuzzy logic-based SVM classifier. With these proposed system, makes it practical to train well performed individual object to its certain face with liveness detection and achieved improvement in performance and accuracy.

The reported success rates for Telugu OCRs are 84-87% for fonts sizes from 12-20 and 95.4-98.5% for sizes from 15 to 35. Some of the issues mentioned in the literature are noise and confusion characters. Studies by the authors have indicated that the touching characters constitute about 1% - 2% of the total characters in printed books of normal size fonts (14 pts). The editable output of OCR System has additional errors due to incorrect code selection emphasizing the need to identify the touching characters. Identification of touching characters is a challenge as the touching may occur at different places due to orthography and rules of grammar. A complete strategy of identification, segmentation and recognition system is proposed along with syllable models for segmentation. Effect of normalization methods at preprocessing stage for improving the identification of touching characters and recognition rates of normal characters is studied. A new algorithm is proposed for segmenting the touching conjunct consonants. The use of augmented database shows clear improvement in the recognition rates. The touching characters are identified and segmented successfully with 83% success rate, thus improving the overall performance of OCR System for Telugu.

In day to day, the Object Liveness Detection for Genuine Face recognition becoming a challenging task in security systems which is important in many real time applications such as User Authentication, Object Identification, Object Recognition, Object live detection, genuine face identification and many more. From many decades, the existing systems and proposed systems for Genuine Object Face recognition and Anti-Spoofing Classifier is accomplished to detect liveness of the object with the help of object features and finds spoofing attacks on all subjects. However, by considering the various individual differences between several objects, the ordinary classifier cannot simplifies well to all objects. In order to overcome this problem, we proposed a Combined HOG-LPQ with Fuz-SVM classifier for Object Liveness Detection, allows to select specific object based on Region of Interest (ROI) and extract features of ROI, so that it will reduce the complexity in feature extraction and then recognises face, later on it check for spoofing attacks using Fuzzy logic based SVM classifier which is specifically trained for each object, and also avoids the interferences between several objects. In addition of all possible rare and uncommon fake samples, the proposed system also includes blur objects. The proposed Combined HOG-LPQ with Fuz-SVM classifier for Object Liveness Detection makes it practical to train well performed individual Object to its certain face with liveness detection. We performed experiments on various real time objects with exiting data base; the details are discussed in the prospect of the proposed approach.

Image analysis mainly focused on identifying the inherent features inside the image for effective understanding of the images. Image segmentation is an integral part of image analysis where, we try to cluster the data and identify meaningful patterns. In this article, we focus upon presenting a model for effective segmentation using non-normal mixture models. The methodology is tested on various image datasets like medical images, natural images, and birds and animals and the result showcases that the model is exhibiting accuracy about 85%, in case of all the images. The performance evaluation carried out using metrics such as image fidelity (IF), peak signal-to-noise ratio (PSNR), and mean squared error (MSE) supports the argument.

Now a days verification has become one of the most important challenges in getting advanced SOC devices in the market. With the advancement of technology, there is a need to integrate more components in SoC that results in increased chip complexity. This complexity issue in SoC must be resolved by some advanced methodology. Industry experts consider that in the overall design effort, the verification effort is almost 70% to 80%. To increase the verification productivity, along with verification language, a proper methodology must be used to facilitate reuse to maximum extent under different design IP configurations. This advanced reusable test bench development increases the availability of a chip in the market. It is helpful in using the same code in sub-block, block and top level as well. This test bench development using advanced verification methodology helps in reducing cost and decreases the time to market for the chip.

growth of mobile users increasing in the present scenario and because of limited bandwidth available, there is a need to efficiently use the bandwidth available. The quality of service can be maximized by efficient bandwidth reservation. In this paper, the cross layer based bandwidth reservation scheme is proposed which initially reserves some amount of bandwidth for handoff flows. After that the bandwidth can be increased for handoff flows by the base station based on the user mobility. The user may not only go straight but also left, right and backwards. This paper considers all possibilities of user movements and bandwidth is reserved accordingly. Therefore making the base stations to dynamically increase the reserved bandwidth for handoffs when the initially reserved bandwidth is insufficient reduces the end to end delay and increases the throughput of the system. The proposed system performance is compared with the legacy systems and is shown to be better.

In recent years Multiple-input multiple-output (MIMO) Multi carrier code division multiple access (MCCDMA), which combines the advantage of diversities with high spectral efficiency has drawn great attention. In this paper we introduce a novel low-complexity multiple-input multiple-output (MIMO) MMSE detector tailored for MCDCDMA systems, suitable for frequency selective channel. The proposed detector begins with estimation of the minimum mean square error (MMSE) on less reliable symbols followed by iterative de-correlation as post-detection processing for mitigating multiple access interferences. Efficient high-throughput VLSI architecture is used to achieve superior performance compared to the conventional MMSE detectors. The performance of the proposed MMSE detector is close to the efficient maximum likelihood, with significant complexity reduction over higher order constellations. The efficiency of MIMO MCCDMA over high order constellations and its quality retentions are verified through MATLAB BER simulation.

We address the issue of performance analysis of fabrication/assembly (F/A) systems, which are systems that first fabricate components and then join the components and subassemblies into a product. Here we consider an F/A system consisting of a single assembly station with input from K fabrication stations. We assume that the system uses a Kanban control mechanism with a fixed number of kanbans circulating between each input station and the assembly station. Even with Markovian assumptions, computing an exact solution for the performance evaluation of such systems becomes intractable due to an explosion in the state-space. We develop computationally efficient algorithms to approximate the throughput and mean queue lengths. The accuracy of the approximations is studied by comparison to exact results (K = 2) and to simulations (K > 2). Part II of this paper demonstrates how these models can be used as building blocks to evaluate more complex F/A systems with multiple levels of assembly stations.

We develop analytical models for performance evaluation of Fabrication/Assembly (F/A) systems. We consider an F/A system that consists of an assembly station with input from K fabrication lines. Each fabrication line consists of one or more fabrication stations. The system is closed with a fixed number of items circulating between each fabrication line and the assembly station. We present algorithms to estimate the throughput and mean queue lengths of such systems with exponential processing times. We then extend our approach to analyze F/A systems with general processing time distributions. Numerical comparisons with simulations demonstrate the accuracy of our approach.

Verification of Gigabit Ethernet Media Access Control (MAC), part of most of the networking SOC is accomplished by using the most advanced verification methodology i.e. Universal Verification Methodology (UVM) has been presented in this paper. The main function of MAC is to forward Ethernet frames to PHY through interface and vice versa. With the use of UVM factory and configuration mechanism, coverage driven verification of MAC Characteristics such as frame transmission, frame reception etc. is achieved in best possible way. Coverage metrics and self-checking which reduces the time spent on verifying design. By using UVM methodology, a reusable test bench is developed which has been used to run different test scenarios on same TB environment.

Verification of Gigabit Ethernet MAC (Media Access Control) by using the most advanced verification methodology i.e. UVM (Universal Verification Methodology) has been presented in this paper. The main function of MAC is to forward Ethernet frames to PHY through XGMII (10 Gigabit Media Independent Interface) and to receive the frames from PHY to MAC through the same interface. Verification of IP provides an elegant way to verify MAC Characteristics such as frame transmission, frame reception etc. Coverage driven verification is best achieved by UVM with the use of factory and configuration mechanism, coverage metrics and self-checking which reduces the time spent on verifying the design. A reusable testbench is developed by using UVM methodology which has been used to run different test scenarios on same TB environment. Regression testing of the design is carried out for achieving better coverage goal.

An n unit system operating in a random environment is considered. The environment determines the number of units required for the satisfactory performance of the system. Assuming that a unit in standby can fail and that the environment is described by a Markov Process, we obtain expressions for (1) the distribution and the moments of the time to the first disappointment and (2) the expected number of disappointments over an arbitrary interval (o, t].

In this paper, an energy efficient design of asymmetric high performance low swing CMOS driver receiver pair for driving global on-chip interconnects is proposed. The design is implemented on 90nm CMOS technology using HSPICE. The proposed CMOS driver receiver pair reduces the power by 35.45% as compared to the static driver with conventional level converter (CLC). The design is also compared with the asymmetric source follower driver with level converter (ASDLC), which results in high performance and low power consumption with reduced circuit complexity. General Terms High performance, low power, circuit complexity, CMOS technology, driver, receiver, interconnect

Security and privacy are major issues which risk the wireless communication system in successful operation employment in Adhoc and Sensor networks. Message confidentiality can be assured through successful message or content encryption, but it is very difficult to address the source location privacy. A number of schemes and polices have been proposed to protect privacy in wireless networks. Many security schemes are offered but none of those provide complete security property for data packets and control packets. This paper proposes a secure policy agreement approach for open-privacy routing in wireless communication using location-centric communication model to achieve efficient security and privacy against both Internal and External adversary pretenders. To evaluate the performance of our proposal we analyze the security, privacy and performance comparisons to alternate techniques. Simulation result shows an improvisation in proposed policy and it is more efficient and offers better privacy when compare to the prior works.

The traditional Indian game of snakes and ladders is played by rolling dice to determine how many squares a player can move his marker up the board, starting at square one and finishing at square one hundred... [there is] an austere geometry of squares broken by angled ladders and snakes with yawning jaws. Landing at the foot of the ladder meant you could climb it, sometimes moving thirty squares in a single throw. You could also make it to square ninety nine, only to encounter a snake.... Then you had to slide down the serpent.

The audio signal is processed in two frequency bands, to detect active and inactive frames present in the audio signal. The voice activity classification of the audio signal is performed depending on the evaluated plurality of parameters and pre-defined validation conditions. The plurality of parameters includes low band energy, high band energy, variance, variance factor, etc. Accurate classification of proposed VAD is evaluated by comparing the bandwidth saving from standard ITU-T G.729B VAD without degrading the voice quality. This bandwidth saving reduces power consumption of a transmitting device, which increases usage time of the battery of the transmitting device.

Routing in adhoc networks is nontrivial due to highly dynamic nature of the nodes. In recent years several routing protocols targeted at mobile adhoc networks are being proposed and prominent among them are DSDV, AODV, TORA, and DSR. This paper does the comprehensive performance analysis of the routing protocols using ns2 simulator considering all the metrics as suggested by RFC 2501. Results indicate reactive routing protocols are more suitable for adhoc networks.

Assuming that a standby unit in a two-unit system has phase type (PH) distribution and all other distributions are arbitrary, the following results are obtained by identifying the suitable regeneration points: 1. 1. reliability of the system 2. 2. availability of the system and 3. 3. interval reliability of the system.

Computer Science deals with information in as much as Physics deals with energy. As Physics deals with energy-transforming devices, Computer Science deals with information transforming devices. The principal enquiries are—effective ways to represent information, effective algorithms to transform information, effective languages to represent these algorithms and effective ways and means to monitor this process and display the so-transformed information. A typical approach to Computerized Information Systems is presented. By defining input, output and control aspects suitably, it can be tailored to specific applications in the medical field.

In this paper the matrix model of an R&D organization developed by Dean (1967) has been extended to organizations with mixed global objectives based on a graph-theoretic formulation. The extended model can be applied to problems like the maximization of R&D outputs of a number of organizations at the level of either a corporation or a country such that a specified growth in the overall research competence of the entire corporation or the country is maintained.