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Simulated Annealing (SA) is one of the most common FPGA placement techniques, and is used both as a standalone algorithm and to improve an initial analytical placement. While SA-based placers can achieve high-quality results, they suffer from long runtimes. In this paper, we introduce RLPlace a novel SA-based FPGA placer that utilizes both Reinforcement Learning (RL) and targeted perturbations (directed moves). The proposed moves target both wirelength and timing optimization and explore the solution space more efficiently than traditional random moves while preventing oscillation in the Quality of Results (QoR). RL techniques are used to dynamically select the most effective move types as optimization progresses. Experimental results show that RLPlace outperforms the widely-used VTR 8 placer across all run-time/quality trade-off points, achieving better QoR placement solutions in less runtime. On average across the Titan23 suite of large FPGA benchmarks, RLPlace can reduce CPU time by 2.5× with result quality comparable to VTR 8, or improve wirelength by 8% (at a high CPU time budget) to 26% (at a low CPU time budget) vs. VTR 8.0 given the same CPU time.

In this paper, a high-sensitivity low-cost power-aware Support Vector Machine (SVM) training and classification based system, is hardware implemented for a neural seizure detection application. The training accelerator algorithm, adopted in this work, is the sequential minimal optimization (SMO). System blocks are implemented to achieve the best trade-off between sensitivity and the consumption of area and power. The proposed seizure detection system achieves 98.38% sensitivity when tested with the implemented linear kernel classifier. The system is implemented on different platforms: such as Field Programmable Gate Array (FPGA) Xilinx Virtex-7 board and Application Specific Integrated Circuit (ASIC) using hardware-calibrated UMC 65nm CMOS technology. A power consumption evaluation is performed on both the ASIC and FPGA platforms showing that the ASIC power consumption is lower by at least 65% when compared with the FPGA counterpart. A power-aware system is implemented with FPGAs by the adoption of the Dynamic Partial Reconfiguration (DPR) technique that allows the dynamic operation of the system based on power level available to the system at the expense of degradation of the system accuracy. The proposed system exploits the advantages of DPR technology in FPGAs to switch between two proposed designs providing a decrease of 64% in power consumption.

As the benefits of Moore's Law diminish, computing performance, and efficiency gains are increasingly achieved through specializing hardware to a domain of computation. However, this limits the hardware's generality and flexibility. Field-programmable gate arrays (FPGAs), microchips which can be reprogrammed to implement arbitrary digital circuits, enable the benefits of specialization while remaining flexible. A challenge to using FPGAs is the complex computer-aided design flow required to efficiently map a computation onto an FPGA. Traditionally, these design flows are closed-source and highly specialized to a particular vendor's devices. We propose an alternate data-driven approach, which uses highly adaptable and retargettable open-source tools to target both commercial and research FPGA architectures. While challenges remain, we believe this approach makes the development of novel and commercial FPGA architectures faster and more accessible. Furthermore, it provides a path forward for industry, academia, and the open-source community to collaborate and combine their resources to advance FPGA technology.

In this paper, a low power support vector machine (SVM) training, feature extraction, and classification algorithm are hardware implemented in a neural seizure detection application. The training algorithm used is the sequential minimal optimization (SMO) algorithm. The system is implemented on different platforms: such as field programmable gate array (FPGA), Xilinx Virtex-7 and application specific integrated circuit (ASIC) using hardware-calibrated UMC 65 nm CMOS technology. The implemented training hardware is introduced as an accelerator intellectual property (IP), especially in the case of large number of training sets, such as neural seizure detection. Feature extraction and classification blocks are implemented to achieve the best trade-off between sensitivity and power consumption. The proposed seizure detection system achieves a sensitivity around 96.77% when tested with the implemented linear kernel classifier. A power consumption evaluation is performed on both the ASIC and FPGA platforms showing that the ASIC power consumption is improved by a factor of 2X when compared with the FPGA counterpart.

In this paper, two different classifiers are software and hardware implemented for neural seizure detection. The two techniques are support vector machine(SVM) and artificial neural networks(ANN). The two techniques are pretrained on software and only the classifiers are hardware implemented and tested. A comparison of the two techniques is performed on the levels of performance, energy consumption and area. The SVM is pretrained using gradient ascent (GA) algorithm, while the neural network is implemented with single hidden layer. It is found that the ANN consumes more power than the SVM by a factor of 4 with almost the same performance. However, the ANN finishes classification in much less number of clock cycles than the SVM by a factor of 34.

In this paper, different window sizes for EEG signal segmentation are investigated in order to optimize the performance of seizure detection systems. To differentiate between epileptic and non-epileptic epochs, the time axis of the EEG signal is divided into non-overlapping windows. The window period should be long enough for the lapse to be informative but not too long for it to stay stationary. Hence, the KPSS test is used to determine signal stationarity for different window sizes, then the optimal window is chosen such that it corresponds to the smallest number of non-stationary segments in the signal of interest. The seizure detection system is then applied to the piece-wise stationary segments. Compared to the exhaustive examination, it is found that the KPSS test optimal window results in the highest sensitivity.

In this paper, both linear and nonlinear features have been reviewed with linear support vector machine (SVM) classifier for neural seizure detection. The work introduced in the paper includes performance measurement through different metrics: accuracy, sensitivity, and specificity of multiple linear and nonlinear features with linear support vector machine (SVM). A comparison is performed between the performance of different combinations between 11 linear features and 9 nonlinear features to conclude the best set of features. It is found that some features enhance the detection performance greatly. Using a combination of 3 features of them, a linear SVM classifier detects seizures with sensitivity of 96.78%, specificity of 97.9%, and accuracy of 97.9%.