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The goal of an automatic monitoring system of partial discharges (PDs), based on acoustic emission (AE) detection, is the identification of the type of source of PD and its localization. In the event that multiple deterioration processes are present in the electrical equipment, more than one PD source may be active and their AE signals may overlap on the sensors. This overlapping effect modifies the temporal and frequency characteristics of the measured signals compared to the characteristics of the signals from a single PD source and thus, automatic classification becomes very difficult. In this paper we have proposed applying blind signal separation (BSS) techniques to recover the signals from each source, therefore separating each temporal and frequency characteristic. We have tested the proposed algorithm: firstly using synthetic mixed signals from two types of PD sources and secondly using real signals from a test bench specifically designed to control the position, time and amplitude of the AEs.

The implementation of a vision system in which the processing core is based on an optoelectronic neural network design is described. The vision system captures an image using a complimentary metal-oxide semiconductor (CMOS) image sensor, and the optoelectronic neural processor performs the classification among a set of sample patterns. The neural-network hardware architecture is based on an optical broadcast of inputs to an electronic array of processing elements, one per class. The benefit of this optoelectronic architecture, and thus the vision application, is that it is potentially scalable to a very large number of processing elements operating in parallel and at very high speed.

On-line identification and classification of voltage and current disturbances in power systems are important tasks in the power quality monitoring and protection of power systems. Some power quality disturbances are non-stationary and transitory while other are steady-state variations that distort the voltage signal. One, two or more different power quality disturbances may appear at the same time. In this paper we propose a power quality monitoring system that employs Independent Component Analysis algorithm that is able to decouple multiple simultaneous power quality disturbances, and Support Vector Machines for identification the occurrence of a disturbance. We also show the first steps towards embedding the proposed system on an FPGA for online power quality monitoring.

We present a successful design for a high-performance, low-resource-consuming hardware for Support Vector Classification and Support Vector Regression. The system has been implemented on a low cost FPGA device and exploits the advantages of parallel processing to compute the feed forward phase in support vector machines. In this paper we show that the same hardware can be used for classification problems and regression problems, and we show satisfactory results on an image recognition problem by SV multiclass classification and on a function estimation problem by SV regression.

In this paper we present a hardware architecture for a Support Vector Machine intended for vision applications to be implemented in a FPGA device. The architecture computes the contribution of each support vector in parallel without performing multiplications by using a CORDIC algorithm and a hardware-friendly kernel function. Additionally input images are not preprocessed for feature extraction as each image is treated as a point in a high dimensional space.

Support vector machines (SVM) present very interesting features in the field of image processing, but the intensive calculation needed complicates its use in real-time applications. We present an architecture for a SVM which simplifies most of the calculus using an optoelectronic matrix-vector multiplier (OMVM).

In this paper we present the scheme for a control circuit used in an image processing system which is to be implemented in a neural network which has a high level of connectivity and reconfiguration of neurons for integration and trigger based on the Address-Event Representation. This scheme will be employed as a pre-processing stage for a vision system which employs as its core processing an Optical Broadcast Neural Network (OBNN). [Optical Engineering letters 42 (9), 2488(2003)]. The proposed vision system allows the possibility to introduce patterns from any acquisition system of images, for posterior processing.

We describe the implementation of a vision system based on a hardware neural processor. The architecture of the neural network processor has been designed to exploit the computational characteristics of electronics and the communication characteristics of optics in an optimal manner, thus it is based on an optical broadcast of input signals to a dense array of processing elements. The vision system has been built by use of a prototype implementation of a neural network processor with discrete optic and optoelectronic devices. It has been adapted to work as a Hamming classifier of the images taken with a 128 x 128 complementary metal-oxide semiconductor image sensor. Its results, performance characteristics of the image classification system, and an analysis of its scalability in size and speed, with the improvement of the optoelectronic neural processor, are presented.

We describe the hardware implementation of a Hamming classifier using an optoelectronic architecture. It is composed of two layers, the first layer is an optoelectronic matrix-vector multiplier based on the optical broadcast architecture; it is a novel architecture composed of a set of electronic neurons that receive the input sequentially by means of an optical broadcast interconnection. The second layer is an electronic winner take all circuit. The main characteristic of the system is that it is readily scalable in speed and size to large numbers of pixel neurons. We will describe the optoelectronic architecture, the hardware implementation of a prototype and evaluation of its performance characteristics.

This paper reports the recent steps to the attainment of a compact high-speed optoelectronic neuroprocessor based on an optical broadcast architecture that is used as the processing core of a vision system. The optical broadcast architecture is composed of a set of electronic processing elements that work in parallel and whose input is introduced by means of an optical sequential broadcast interconnection. Because of the special characteristics of the architecture, that exploits electronics for computing and optics for communicating, it is readily scalable in number of neurons and speed, thus improving the performance of the vision system. This paper focuses on the improvement of the optoelectronic system and electronic neuron design to increase operation speed with respect to previous designs.

This paper reports the recent steps to the attainment of a compact high-speed optoelectronic neuroprocessor based on an optical broadcast architecture. The optical broadcast architecture is composed of a set of electronic processing elements that work in parallel and whose input is introduced by means of an optical sequential broadcast interconnection. Because of the special characteristics of the architecture, that exploits electronics for computing and optics for communicating, it is readily scalable in number of neurons and speed. This paper focuses on the improvement of the optoelectronic system and electronic neuron design to increase operation speed with respect to previous prototype.

In this paper we propose of a novel hardware electronic-optoelectronic neural network processor for vision applications. The architecture of the proposed neuroprocessor is based on a hybrid optic and optoelectronic implementation of the system. Some neural operations, like interconnection weight storage and assignment, are done in the electronic domain while the interconnection between processing elements is done optically. By this way we exploit the communication strength of optics and the computational strength of electronics in an optical fashion. The main characteristics of the architecture are that it is fully interconnected, the interconnections are fully programmable, it avoids optical alignment problems, and it is readily scalable to large numbers of pixel neurons. We will describe the architecture, the hardware implementation of a first prototype and its functionality for pattern recognition applications. The neural network models we have implemented on our neuroprocessor have been a basic logic functions operator, a Hopfield network and the matching scores layer of a Hamming network.

We describe the concept of a vision system based on an optoelectronic hardware neural processor. The proposed system is composed of a pulse coupled neural network (PCNN) preprocessor stage that converts an input image into a temporal pulsed pattern. These pulses are inputs to the optical broadcast neural network (OBNN) processor, which classifies the input pattern between a set of reference patterns based on a pattern matching strategy. The PCNN is to provide immunity to the scale, rotation, and translation of objects in the image. The OBNN provides high parallelism and a high speed hardware neural processor.

A novel, compact optoelectronic hardware neural network ar- chitecture based on an optical broadcast scheme is proposed and dem- onstrated. The basic cell in the system is composed of electronic neu- rons that share the same time-distributed, optical broadcast input. The system combines the computational strengths of electronics and the communication strengths of optics, and employs a modular reconfig- urable architecture that is potentially scalable to a very large number of neurons while maintaining compactness. These characteristics are real- ized in an architecture that combines the integration of the processing elements in complementary metal-oxide semiconductor (CMOS) tech- nology with the construction of efficient optical interconnection elements with focusing properties based on multiplexed volume holograms. © 2005 Society of Photo-Optical Instrumentation Engineers. (DOI: 10.1117/1.1902994) Subject terms: optical neural networks; complementary metal-oxide semiconduc- tor sensor arrays; electronic processing; optical interconnects; volume holograms.

We present the first implementation, results, and performance analysis of a vision system whose processing core is a prototype hardware neural network based on an optical broadcast architecture. The system captures an im- age by a CMOS image sensor, compares it with a set of sample patterns (classes), and provides an output that indi- cates the class which the input image corresponds to. Due to the optoelectronic neural processor characteristics, the num- ber of classes can be enlarged without penalty on the opera- tion speed of the system. © 2004 Society of Photo-Optical Instru

A new optoelectronic hardware architecture of a neural network processor is proposed. A basic cell in the system is composed of electronic neurons that share the same time-distributed input; the input is introduced by means of an optical broadcast. The system combines the computational strength of electronics and the communica- tion strength of optics in an optimal manner and it is poten- tially scalable to a very large number of neurons. A descrip- tion of the system is given and the behavior of a first prototype is shown. © 2003 Society of Photo-Optical Instrumentation