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While complete automated design is a harder problem than computer-assisted design, automated hardware reconfiguration is an even more challenging problem, because it needs to adjust to limited resources and various factors, such as noise and parasitic capacitance, a resistance and inductance. This paper presents some experimental results of on-chip automated design and reconfiguration using evolvable hardware techniques. It describes a stand-alone board level evolvable system, and its use to demonstrate on-chip synthesis of new circuits in only a few seconds. The experiments presented here indicate a recovery capability in the case of extreme environmental conditions, such as extreme temperatures, that adversely affect electronics. Some of the difficulties of dealing with the real hardware are exposed, as well as challenges more generally related to automated evolution of complex electronic systems.

We propose a tuning method for Micro-Electro-Mechanical Systems (MEMS) gyroscopes based on evolutionary computation to increase the accuracy of MEMS gyroscopes through electrostatic tuning. The tuning method was tested for the second generation JPL/Boeing Post-resonator MEMS gyroscope using the measurement of the frequency response of the MEMS device in open-loop operation. We also report on the development and preliminary results of a hardware platform for integrated tuning based on “switched drive-angle” of MEMS gyroscopes whereby the same gyro is operated with its drive direction first at 0° and then at 90°. The control of this device is implemented through a digital design on a Field Programmable Gate Array (FPGA). The hardware platform easily transitions to an embedded solution that allows for the miniaturization of the system to a single chip.

We propose a tuning method for MEMS gyroscopes based on evolutionary computation to efficiently increase the sensitivity of MEMS gyroscopes through tuning. The tuning method was tested for the second generation JPL/Boeing Post-resonator MEMS gyroscope using the measurement of the frequency response of the MEMS device in open-loop operation We also report on the development of a hardware platform for integrated tuning and closed-loop operation of MEMS gyroscopes. The control of this device is implemented through a digital design on a Field Programmable Gate Array (FPGA). The hardware platform easily transitions to an embedded solution that allows for the miniaturization of the system to a single chip.

Evolvable systems in silicon are third generation hardware in terms of flexibility and fault-tolerance. The first generation was fixed silicon: once a device was fabricated its structure was forever fixed. Reconfigurable hardware came as a second generation: new configurations could be downloaded changing the function of the device and also bypassing faulty areas, if any. The third generation is that of self-configurable, evolvable hardware (EHW), and adds the automatic reconfiguration feature, enabling truly adaptive hardware. This chapter addresses current efforts in building and using evolvable chips. The first section refers to evolutionary algorithms for evolvable hardware. The second section describes the JPL evolvable hardware testbed and the JPL Field Programmable Transistor Array (FPTA) chip designed and used for circuit evolution in silicon. The third section addresses the application of evolvable hardware for adaptive filtering and noise cancellation. The fourth section discusses the importance of fault-tolerant hardware in space and describes the evolvable hardware approach for faulttolerant design of a 4-bit data converter. The final section concludes the work.

Evolvable systems in silicon are third generation hardware in terms of flexibility. The first generation was fixed silicon: once a device was fabricated its structure was forever fixed. Reconfigurable hardware came as a second generation: new configurations could be downloaded changing the function of the device and also bypassing faulty areas, if any. The third generation is that of self-configurable, evolvable hardware (EHW), and adds the automatic reconfiguration feature, enabling truly adaptive hardware. This paper addresses current efforts in building and using evolvable chips. The first section refers to evolutionary algorithms for evolvable hardware. The second section describes the JPL evolvable hardware testbed and the JPL Field Programmable Transistor Array (FPTA) chip designed and used for circuit evolution in silicon. The third section addresses the application of evolvable hardware for signal separation and noise cancellation. The final section concludes the work.

The paper presents some experiments in automatic reconfiguration of field programmable devices using evolutionary algorithms. The experiments use a Field Programmable Transistor Array (FPTA), reconfigurable at transistor level. While parasitic effects of imperfect switches interconnecting transistors deteriorate performance of conventional designs when mapped to the FPTA, evolutionary algorithms are able to find a working design solution. The experiments are performed with a stand-alone board-level evolvable system (SABLES) in which the evolutionary algorithm is implemented with a DSP. SABLES can automatically configure the FPTA in tens to hundreds of seconds, time in which evaluates /spl sim/100,000 circuit candidate solutions. The paper overviews some examples of evolutionary synthesis of analog circuits on the FPTA.

This paper comments on some directions of growth for evolvable hardware, proposes research directions that address the scalability problem and gives examples of results in novel areas approached by EHW. The directions of growth include Software/Hardware hybrids, electronic/non-electronic hybrids, and networked systems. The research directions proposed here are (1) evolutionary compilation of descriptions from behavioral Hardware Description languages (HDL) to structural HDL (for both the case of digital and analog/mixed signal) (2) evolutionary synthesis, i.e. converting from synthesizable HDL to circuits and (3) hardware-software partitioning (co-design) for CPU/FPGA hybrids. The results presented here illustrate evolutionary design of multi-junctional/adaptive circuits including polymorphic and reconfiguration based circuits, and evolution of optimized circuits, in particular low-voltage circuits.

Evolutionary algorithms (EA) offer good promise for automated design of analog circuits as well as for adaptation and automatic reconfiguration of programmable devices. In particular, EAs facilitate the design of analog circuits for very specific requirements, such as those related to the implementation of fuzzy operators, or even of complete fuzzy systems. The paper starts with a brief overview of the evolutionary process applied to circuit design and of a family of analog programmable devices that support on-chip evolution. As a case study, we describe the evolutionary design of a fuzzy controller, using re-configurable analog chips models and unstructured representation. We were able to achieve a circuit that approximates the control surface of a 2-input fuzzy controller, mapping thus a full fuzzy system in only seven transistors. The paper presents evidence that EA can provide very compact solutions for implementation of fuzzy systems, and that programmable analog devices are an efficient and rapid solution for rapid deployment of fuzzy systems.

Evolvable hardware provides the capability to evolve analog circuits to produce amplifier and filter functions. Conventional analog controller designs employ these same functions. Analog controllers for the control of the shaft speed of a DC motor are evolved on an evolvable hardware plaform utilizing a Field Programmable Transistor Array (FPTA). The performance of these evolved controllers is compared to that of a conventional proportional-integral (PI) controller. It is shown that hardware evolution is able to create a compact design that provides good performance, while using considerably less functional electronic components than the conventional design.

In this paper we describe the hardware evolution of analog circuits performing signal separation tasks using JPL's Stand-Alone Board-Level Evolvable System (SABLES). SABLES integrates a Field Programmable Transistor Array chip (FPTA-2) and a Digital Signal Processor (DSP) implementing the Evolutionary Platform (EP). The FPTA-2 is a second generation reconfigurable mixed signal array chip whose cells can be programmed at the transistor level. Its chip architecture consists of an 8×8 matrix of reconfigurable cells. The FPTA-2 is reconfigured by evolution to achieve circuits that can extract a target signal that is combined with an undesired component or to perform the separation of a combination of two signals. The paper considers also an adaptive filter where the fitness function depends on the input signal. The results demonstrate that SABLES is not only able to perform signal separation and extraction, but it is also flexible enough to adapt to different input signals without human intervention, such as in the case of self-tuning and adaptive filters.