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Crystal structures are always considered as origin of properties of dielectric materials, which poses importance for microscopic observation, especially for materials with peculiar local structures. Convergent beam electron diffraction (CBED) is a widely used informative method of reading crystal structure. However, identifying CBED images by traditional artificial methods is a time-consuming process accompanied with certain ambiguity, which limits its application. Here, we identify CBED images by artificial intelligence methods to solve that problem. The method includes segmenting patterns and analyzing mirror symmetry of CBED images. Canny edge detection and Hough transform are used to divide CBED patterns into discs individually, which can successfully extract common key information of all CBED images. Then the direct grey level symmetry similarity evaluation (DGLS) and texture symmetric similarity detection method based on principal component analysis (TSPCA) are both calculated to estimate mirror symmetry performance quantitatively. The average matching rate of accuracy between computer calculation and visual inspection is 96.0% for DGLS and 97% for TSPCA. This method provides a uniform standard for mirror symmetry identification and is more conducive and objective to the analysis of a large number of experimental CBED images, which is of great significance to promote the further research of reading local structure for ferroelectric ceramic.

Due to the increased complexity of modern embedded systems and time-to-market constraints, a debugger with efficient debugging functions is becoming increasingly necessary, and it plays an important role in the development of application systems. Accordingly, the implementation of efficient debug functionalities must a critical process in the design of a new processor. Since deeply embedded processor cores in a core-based system chip allow only restricted access for debugging its internal status, most recent processors employ the on-chip-based debug method that embeds special logic-supporting debug capabilities. In this paper, we propose an on-chip debug support logic that can be embedded into the processor core to support debug functions. Moreover, we describe an overall implementation method of the on-chip-based processor debugger based on the on-chip debug support logic, which includes a source-level debugger and an interface block. We designed an on-chip debug support logic, and embedded it into a target processor core. We used the GNU Project debugger (GDB) as the source-level debugger of the target processor core. An interface block that uses the remote debugging features of GDB was also developed and that includes a software module and a hardware board. We discuss all major design steps for implementing this on-chip-based processor debugger. We have successfully applied the proposed implementation method to develop the processor debugger for two new 32-bit RISC processors. In addition, we introduce another use of the on-chip-based processor debugger in the design of a processor-based system chip, which can facilitate simulation-based functional verification.

Recently smart devices which combine traditional electronic devices and personal computers, such as smart phones and smart TV, have caught people`s eyes from all over the world. A multi-media SoC platform which embeds not only a calculating processor but also an operating system could provide an user-customized environment of several types of communication methods to PC or Internet. In this paper, we describe a multi-functioning SoC platform with video, audio and other communicating protocols based on Core-A processor and AMBA buses. To verify the designed multi-media SoC platform, JPEG decoding and ADPCM encoding/decoding algorithms are applied on it and the final decoding results are confirmed by video monitors and audio speakers.

Nowadays, the multicore processor is watched with interest by people all over the world. As the design technology of system on chip has developed, observing and controlling the processor core’s internal state has not been easy. Therefore, multicore processor debugging is very difficult and time-consuming. Thus, we need a reliable and efficient debugger to find the bugs. In this paper, we propose an on-chip debug architecture for multicore processors that is easily adaptable and flexible. It is based on the JTAG standard and supports monitoring mode debugging, which is different from run-stop mode debugging. Compared with the debug architecture that supports the run-stop mode debugging, the proposed architecture is easily applied to a debugger and has the advantage of having a desirable gate count and execution cycle. To verify the on-chip debug architecture, it is applied to the debugger of the prototype multicore processor and is tested by interconnecting it with a software debugger based on GDB and configured for the target processor.

Because of the intrinsic lack of internal-system observability and controllability in highly integrated multicore processors, very restricted access is allowed for the debugging of erroneous chip behavior. Therefore, the building of an efficient debug function is an important consideration in the design of multicore processors. In this paper, we propose a flexible on-chip debug architecture that embeds a special logic supporting the debug functionality in the multicore processor. It is designed to support run-stop-type debug functions that can halt and control the execution of the multicore processor at breakpoint events and inspect the possible causes of any errors. The debug architecture consists of the following three functional components: the core debug support block, the multicore debug support block, and the debug interface and control block. By embedding this debug infrastructure, the embedded processor cores within the multicore processor can be debugged simultaneously as well as independently. The debug control is performed by employing a JTAG-based scanning operation. We apply this on-chip debug architecture to build a debugger for a prototype multicore processor and demonstrate the validity and scalability of our approach.

 Abstract—Nowadays, the SoC is concentrated by all over the world with interest. The design trend of the SoC is hardware and software co-design which includes the design of hardware structure in RTL level and the development of embedded software. As the complexity of SoC design increases with technology development, the observability of the SoC's internal state is no longer easy to achieve. Because of the above reasons, debugging the SoC system becomes very difficult and time-consuming. So we need a reliable debugger to find the bugs in the SoC and embedded software. In this paper, we deal with implementation of a hardware debugger named OCD2G which is based on IEEE 1149.1 JTAG standard and supports halt-mode and monitoring-mode debugging. In order to verify the operation of OCD2G, the designed debugger is integrated into the 32bit RISC processor - Core-A (Core-A is an embedded processor designed in South Korea) and is tested by interconnecting with software debugger.

Bio-signal processor platform system carries out the bio-signal processing extracted from array sensors. This system consists of 32-bit RISC processor, data converter circuit, array sensors and bio-signal processing algorithm. The designed specific processor includes CPU functional blocks and memory. Array sensors measure a variation of capacitance value by reaction with DNA, aptamer and protein. Processor reduces noise component from measured bio-signal and compares and detects disease by analyzing properties of bio-signals.

In this paper, we introduce on-chip debug system (OCDS) which supports symbolic debugging at c-level using OCD integrated Debug-logic into target processor. The OCDS consist of SW debugger that supports a functionality of symbolic debugging, OCD (on-chip debugger) serving as a debugger of internal state of target processor, and Interface & Control block interfacing SW debugger and OCD. After OCD block is interfaced with 32 bit RISC processor core and then implemented with FPGA, OCD is connected by Interface & Control block, and SW debugger. The verification of the design is carried out through device recognition, carrying-out instructions of JTAG(joint test action group), reading and writing the internal registers of the processor and memory, and checking the emulation functions such as setting break-points and watch points.

The procedure of design and verification for a 16-bit RISC processor is introduced in this paper. The proposed processor has Harvard architecture and consists of 24-bit address, 5-stage pipeline instruction execution, and internal debug logic. ADPCM vocoder and SOLA algorithm are successfully carried out on the processor made with FPGA.