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With the deployment of wide-area measurement systems (WAMS) equipment, dynamic security assessment (DSA) based on artificial intelligence (AI) has more and more advantages. For the power system, the number of transient stable cases is much larger than that of unstable cases, which leads to insufficient learning of unstable cases and affects the evaluation effect of the model. In addition, during the stability assessment process of the power system, the misjudgment cost of unstable case is much higher than that of stable case. Based on the above two points, we proposed a DSA method of power system based on improved XGBoost. The proposed method introduces the weight adjustment factor into the loss function to balance the quantity variance of two type cases and the difference of misjudgment cost, which greatly reduces the misjudgment rate of unstable samples. The test results on IEEE 16-machine 68-bus test system and IEEE 50-machine 145-bus test system show that the proposed method can have higher recognition of the unstable samples and can be applied to DSA.

This work focuses on resolving high ESR issue in standard MIM templates. The solutions have been deployed to tens-of-Gbps high-speed serial links to minimize power noise and supply-induced jitter. New aspects of this work are: (1) MIM templates and their associated power/ground grid are optimized to minimize ESR and achieve good area utilization. These modular designs allow simplicity and flexibility in implementation. (2) Accurate ESR calculation methodology for simple MIM structures is developed. It correlates well with layout extraction using commercial tools.

This paper investigates the performance benefit of using nonuniformly quantized ADCs for implementing high-speed serial receivers with decision-feedback equalization (DFE). A way of determining an optimal set of ADC thresholds to achieve the minimum bit-error rate (BER) is described, which can yield a very different set from the one that minimizes signal quantization errors. By recognizing that both the loop-unrolling DFE receiver and ADC-based DFE receiver decide each received bit based upon the result of a single slicer, an efficient architecture named reduced-slicer partial-response DFE (RS-PRDFE) receiver is proposed. The RS-PRDFE receiver eliminates redundant or unused slicers from the previous DFE receiver implementations. Both the simulation and measurement results from a 10 Gb/s ADC-based receiver fabricated in 65 nm CMOS technology and multiple backplane channels demonstrate that the RS-PRDFE can achieve the BER of a 3-4-bit uniform ADC only with 4 data slicers. Also, the combined use of linear equalizers (LEs) can further reduce the required slicer count in RS-PRDFE receivers, but only when the LEs are realized in analog domain.

Accurate analysis of link performance including deterministic and random effects as well as advanced signal conditioning schemes is crucial in modern high-speed I/O design. In recent years, statistical link performance tools such as LinkLab and StatEye are introduced to efficiently analyze the overall link performance with both deterministic and random noise. The statistical-domain analysis has limitations in terms of its capability of accurately simulating system nonlinearity, jitter, as well as coding. In this paper, we present a new hybrid approach that combines statistical and time-domain techniques to efficiently overcome these limitations. The proposed method has several key contributions: 1) capture system nonlinearity; 2) separately simulate short-term deterministic jitter in the time domain and long-term deterministic and random jitter in the statistical domain; 3) co-simulate clock and data channels to capture jitter tracking; and 4) co-simulate signal and power integrity to include simultaneous switching output noise. We demonstrate this hybrid approach by studying the jitter tracking capability of a clock forwarding scheme and the effectiveness of coding in terms of system bit error rate.

Clocked comparators have found widespread use in noise sensitive applications including analog-to-digital converters, wireline receivers, and memory bit-line detectors. However, their nonlinear, time-varying dynamics resulting in discrete output levels have discouraged the use of traditional linear time-invariant (LTI) small-signal analysis and noise simulation techniques. This paper describes a linear, time-varying (LTV) model of clock comparators that can accurately predict the decision error probability without resorting to more general stochastic system models. The LTV analysis framework in conjunction with the linear, periodically time-varying (LPTV) simulation algorithms available from RF circuit simulators can provide insights into the intrinsic sampling and decision operations of clock comparators and the major contribution sources to random decision errors. Two comparators are simulated and compared with laboratory measurements. A 90-nm CMOS comparator is measured to have an equivalent input-referred random noise of 0.73 mVrms for dc inputs, matching simulation results with a short channel excess noise factor ? = 2.

High-speed input/output (I/O) link performance is limited by random noise as well as signal integrity issues such as dispersion, reflections, and crosstalk. Hence, accurate prediction of system performance including these random and deterministic noise is crucial in high-speed link design. This paper presents a novel, fast, and accurate method to simulate the time-domain system response. The presented method calculates the system response using multiple edge responses (MER) based on linear superposition. Being able to take into account system nonlinearity more accurately, the presented method significantly improves simulation accuracy compared with the other published fast simulation techniques based on either single bit response (SBR) or double edge responses (DER), while at the same time maintaining equivalent numerical efficiency. Furthermore, peak distortion analysis, which is commonly used to find the worst-case data pattern based on SBR, is extended for DER and MER using dynamic programming. A multiphase worst-case data pattern approach is also introduced in this paper in order to determine the worst-case system performance under both timing and voltage consideration.

Accurate analysis of system timing and voltage margin including deterministic and random jitter is crucial in high-speed I/O system designs. Traditional SPICE-based simulation techniques can precisely simulate various deterministic jitter sources, such as intersymbol interference (ISI) and crosstalk from passive channels. The inclusion of random jitter in SPICE simulations, however, results in long simulation time. Innovative simulation techniques based on a statistical simulation framework have been recently introduced to cosimulate deterministic and random jitter effects efficiently. This paper presents new improvements on this statistical simulation framework. In particular, we introduce an accurate jitter modeling technique which accounts for bounded jitter with arbitrary spectrum in addition to Gaussian jitter. We also present a rigorous approach to model duty cycle distortion (DCD). A number of I/O systems are considered as examples to validate the proposed modeling methodology.

A SerDes operating at 40 Gb/s optimized for chip-to-chip communication is presented. Equalization consists of 2-tap feed-forward equalizers (FFE) in both transmitter and receiver, a 3-stage continuous-time linear equalizer (CTLE) and discrete-time equalizers including a 17-tap decision feedback equalizer (DFE) and a 3-tap sampled-FFE in the receiver. The SerDes is realized in 28-nm CMOS technology with 23.2 mW/Gb/s power efficiency at 40 Gb/s.

A 4×40 Gb/s collaborative digital CDR is implemented in 28nm CMOS. The CDR is capable of recovering a low jitter clock from a partially-equalized or un-equalized eye by using a phase detection scheme that inherently filters out ISI edges. The CDR uses split feedback that simultaneously allows wider bandwidth and lower recovered clock jitter. A shared frequency tracking is also introduced that results in lower periodic jitter. Combining these techniques the CDR recovers a 10GHz clock from an eye containing 0.8UIpp DDJ and still achieves 1-10 MHz of tracking bandwidth while adding

A new 1-tap predictive decision feedback equalizer (prDFE), implemented in 40-nm CMOS LP process, achieves 27-Gb/s operation with 0.41-mW/Gb/s power efficiency. The prDFE employs a novel quad-data rate sampling architecture to improve power efficiency while minimizing critical feedback path timing constraint of the equalizer to enable post-cursor inter-symbol interference (ISI) cancellation at high data-rate operations.

High-speed link design in a 3D package system poses unique challenges due to the fact that it provides limited visibility to signal quality and that supply noise induced jitter is large due to a poor power distribution network in a small form factor. This paper outlines a statistical link simulation flow to accurately capture the impact of timing jitter due to power supply noise in 3D systems. The analysis includes on-chip jitter accumulation and link-level jitter tracking by considering both passive channel and on-chip signal path. On-chip measurement techniques which allow in-situ testing of the overall link margin are also described.

As data rate pushes to 10Gbps and beyond, timing jitter has become one of the major factors that limit the link performance. Thorough understanding of the link jitter characteristics and accurate modeling of their impact on link performance is a must even at early design stage. This paper discusses the characteristics of timing jitter in typical I/O interfaces and overviews various jitter modeling methods proposed in the literature during the past few years. Recommendations are given based on the characteristics of timing jitter and their locations.

A 5Gb/s signaling system was designed and fabricated in TSMC's 40nm LP CMOS process. A new clock/data skew minimization technique with a source-synchronous transmit clock delay line and integrating receiver tolerates high frequency transmit clock jitter and supports rapid turn-on without the clock buffer latency of conventional source-synchronous systems. A second method to minimize clock distribution via embedded clocking with superposition of clock in the common-mode was also explored.

Single-ended signaling systems, popular in memory I/O interfaces, are limited by signal and power integrity issues such as crosstalk and simultaneous switching output noise (SSO). At high data rates, the single-ended systems also suffers from random noise and timing jitter. In this paper, we present an integrated signal and power integrity simulation flow that combines statistical and transient simulation methods to enable the characterization of single-ended systems to account for random timing jitter in addition to the traditional SI issues focused on the deterministic noise such as intersymbol interference (ISI), crosstalk, and SSO noise. To include SSO noise, we co-simulate power distribution network (PDN) and channel models and treat SSO noise as another form of crosstalk. To capture any system nonlinearity, we employ time-domain based multi-edge response (MER) method to characterize the deterministic and passive portion of channels. Then, random noise and timing jitter impact are included via statistical approach. We use GDDR system to demonstrate our simulation flow.

Clocked comparators have found widespread use in noise sensitive applications such as wireline receivers, A/D converters, and memory bit-line detectors. However, their nonlinear, time-varying behavior and discrete output levels have discouraged the use of traditional small-signal noise simulation techniques such as NOISE in SPICE. This paper asserts that the periodic noise analysis available from RF circuit simulators can provide insight into the intrinsic sampling and decision operations of clocked comparators and help develop a linear periodically time-varying (LPTV) noise model that accurately predicts the decision error probability. Two comparators are simulated and compared to laboratory measurements. A 90 nm CMOS comparator is measured to have an equivalent input-referred random noise of 0.73 mVrms for DC inputs, matching simulation results with a short channel excess noise factor gamma = 2.

Conventional ways of summing component specifications to balance voltage and timing budgets are increasingly problematic as data rates continue to scale higher for high speed links. For instance, performance degradation caused by transmitter jitter is more severe than that caused by receiver jitter due to jitter coloring by the passive channel. Furthermore, certain jitter components could interact in the system so it is inaccurate to treat them as independent variables. A system voltage and timing budgeting process hence requires a sophisticated method to accurately predict the overall system performance based on the component specifications. With the recent introduction of a statistical CAD tool, the impact of each individual component, including both deterministic and random jitter, can be co-simulated [l]-[3]. This paper demonstrates the usage of this statistical CAD tool for modeling component budgets. We verify the accuracy of our modeling approach by correlating with a FlexIOreg parallel link interface. Then, we apply the proposed methodology to a PCI Expressreg bus system to estimate the system performance based on published component jitter specification.

To achieve multi-Gb/s data rates over backplane channels, equalization is required to compensate for the non-idealities of the channels. In this paper, we first show that with decision-feedback equalization (DFE) handling postcursor inter-symbol interference (ISI), cancelling precursor ISI with transmitter equalization degrades rather than improves performance for most channels. This is due to the interaction between equalization adaptation and clock-data recovery (CDR), coupled with transmitter peak-power constraint. To minimize the impact of precursor ISI on the bit-error-rate (BER), we propose a new method of adapting CDR phase for maximum voltage margin.

A long chain of inverters and wire segments will amplify clock jitter and drop timing pulses due to intersymbol interference. We present a jitter attenuating buffer based on surfing techniques. Our buffer circuit consists of a few inverters with variable output strength that implement a simple, low-gain DLL. Chains of these surfing buffers attenuate jitter making them well suited for source-synchronous interfaces. Furthermore, our chains can be used to reliably transmit handshaking signals and support sliding-window protocols to improve the throughput of asynchronous communication.

We present a novel method for jointly optimizing FIR filters for pre-equalization, decision feedback equalization, and near-end crosstalk cancellation. The unified optimization problem is a linear program, and we describe sparse matrix techniques for its efficient solution. We illustrate our approach with uni- and bi-directional buses using differential signaling in both intra-board and cross-backplane scenarios.

We present a method for synthesizing crosstalk cancelling equalization filters for off-chip buses. Our approach is based on linear programming and allows direct optimization of the eye mask as well as controlling maximum filter output and maximum overshoot at the receiver. While the linear program formulation is flexible and straightforward, the resulting linear programs are quite large. We present an implementation of Mehrotra’s interior point method that exploits the structure and sparsity of our problem, enabling the practical synthesis of filters for large buses. As an example, we show a 32-bit bit bus with tight wire spacings. Using our filters, we achieve 7.5 times the bandwidth of a bus with no equalization, and 5 times the bandwidth of a bus with single-line pre-emphasis.