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The volume of data is increasing day by day. For data transmission photon has already replaced the electron, but still at transmit and receive ends, devices lose energy while converting electrons into photon and back. So, the concept of optical gates might be a potential resource in the future. In this paper, we theoretically design a two input Arithmetic Logic Unit (ALU) that computes addition, subtraction, AND, OR, XOR operations separately and simultaneously. For design and implementation of optical logic gates Polarized-Encoded Optical Shadow Casting (POSC) algorithm is utilized. Three planes are considered here: source plane, input plane, and output plane. In source plane incoherent Light-Emitting Diode (LED) array works as the light source. We designed the scheme for input pixel, then overlapped those two pixel patterns at the input plane and finally illuminated the overlapped pixel pattern on output screen by light emitting diodes of source plane. By altering the minterm group, various input coding patterns are being calculated. Several equations are obtained from truth table for required operations.

while the last 30 years has seen the computer industry driven primarily by faster uni-processors those days have come to an end. Emerging in their place are multi processors containing multiple processor cores that are expected to exploit parallelism (3), (4). High reliability, availability and scalability (2)needs efficient multistage switching network to ensure performance (throughput) improvement. Current advancement in IC technology has helped us to design Universal Functional\ Block for these different interconnection networks. Here in this\ paper we have designed a Universal Block for hypercube interconnection network using two different approaches indirect hypercube switching and shuffle exchange switching simultaneously. Index Terms: Universal Functional Block, Indirect Hypercube, Shuffle Exchange, Omega switching.

Efficient parallel schemes for carry-propagation-free addition of modified signed-digit trinary numbers are presented. The necessary minterms for implementation using an optical programmable logic array area are derived. The proposed schemes require only a truth table of 25 entries compared with an earlier scheme of 625 entries. The proposed schemes are amenable to optical implementation. Experimental results using an optical programmable logic array are demonstrated. The experiments show the problems of noise and crosstalk. This suggests some dc bias is necessary to increase the signal-to-noise ratio of the optical circuit.

A 2-bit trinary full adder using a restricted set of a modified signed-digit trinary numeric system is designed. When cascaded together to design a multi-bit adder machine, the resulting system is able to operate at a speed independent of the size of the operands. An optical non-holographic content addressable memory based on binary coded arithmetic is considered for implementing the proposed adder.

A memory-efficient dual cell and a multioutput parallel arithmetic logic unit are designed by using a polarization-encoded optical shadow-casting scheme. The design algorithms for identifying the source patterns, input encoding, and output mask are also presented.

A memory-efficient arithmetic logic unit (ALU) consisting only of two cells has been designed using a polarization-encoded optical shadow truth table partitioning scheme. The design algorithm for identifying the source patterns, input encoding, and output decoder with possible parallel implementation are also presented.

An efficient multiprocessor has been designed using a polarization-encoded optical shadow casting truth table partitioning scheme. As an example, the design algorithm for identifying the source patterns, input patterns, and output mask for the design of an adder-subtracter is presented.

A memory-efficient multioutput arithmetic logic unit has been designed using a polarization-encoded optical shadow casting scheme. The authors expand the scope of special-purpose optical digital computing to more general-purpose computing. Consequently, a novel design of an arithmetic logic unit (ALU) is proposed which is capable of performing both arithmetic and logical operations. A conventional ALU architecture is followed, where the output of the ALU are generated separately. Normally, all the outputs of an ALU are not required at the same time. Thus sequential output generation is not a bottleneck. The design algorithms for identifying the source patterns, input encoding, and output mask are presented. >

A high speed parallel full adder is designed which can perform carry-free addition of two modified signed digit quaternary numbers. For digital implementation, the sign digit quaternary numbers are represented using 3-bit 2's complement notation. The adder truth table with possible schemes of the electronic and optical implementation are provided. >

An efficient carry-free addition and borrow-free subtraction of modified signed-digit trinary number scheme is presented which may be used for parallel computing application. A digital 2 bit prototype adder was designed and implemented using electrically programmable logic device (EPLD). >