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With continually growing adoption of FPGA based designs, and more features and capabilities available in FPGAs, board and system level test applications can - and should - take advantage of FPGA embedded instrumentation. Such FPGA assisted tests not only improve manufacturing test but also allow extensive testing in the field to address issues such as no-fault-found syndrome by enabling the detection of environment-induced defects or latent defects (related to bad solder joint quality, aging, etc.). In this paper we are briefly reviewing different types of FPGA embedded instruments before specifically addressing synthetic instrumentation and focusing on example use cases. We will be discussing design for test considerations, quality of test and diagnostics, savings in test time and test cost, and levels of automation previously not associated with functional and performance / stress test development.

This chapter further details the topic of embedded self-test directing the reader towards the aspects of embedded test generation and test sequence optimization. The authors will brief the basics of widely used pseudorandom test generators and consider different techniques targeting the optimization of fault coverage characteristics of generated sequences. The authors will make the main focus on one optimization technique that is applicable to reseeding-based test generators and that uses a test compaction methodology. The technique exploits a great similarity in the way the faults are covered by pseudorandom sequences and by patterns generated for sequential designs. Hence, the test compaction methodology previously developed for the latter problem can be successfully reused in embedded testing.

LFSR reseeding techniques are often applied in BIST due to their ability to considerably improve the fault coverage and test application time by embedding specific vectors into the pseudorandom sequence. The efficiency of a typical reseeding scheme to a large extent depends on the seed selection and consequent test sequence optimization algorithms. This paper proposes a novel efficient reseeding optimization algorithm that is based on test compaction techniques for sequential designs. The proposed approach relies on the branch-and-bound search technique, which can provide the optimal test set compaction solution for a given test setup. Alternatively, it can run for a limited time in a heuristic mode, producing intermediate results. Experiments show that applied heuristics can yield optimal or quasi-optimal solutions in polynomial time. These solutions outperform previously published reseeding and hybrid BIST results.

This paper describes a new software tool for high quality training/learning in the field of digital microelectronics. Its main purpose is to give insight into reliability and quality assurance technologies based on linear feedback shift registers (LFSR) and other pseudo-random pattern generators (PRPG). Various PRPG types are becoming the mainstream test generation solution used in built-in self-test (BIST) structures. Taking into account complex theoretical concepts behind the microelectronics self-testing (including data coding and compression, cryptography, field theory, linear programming) it is important to effectively educate engineers in this field. The software tool we present in this paper is aimed at facilitating this goal. Unlike other similar systems, this tool facilitates study of various test optimization problems, allows fault coverage analysis for different circuits and with different LFSR parameters. The main didactic aim of the tool is presenting complicated concepts in a comprehensive graphical and analytical way. The multi-platform JAVA runtime environment allows for easy usage of the tool both in the classroom and at home. The BIST Analyzer represents an integrated simulation, training, and research environment that supports both analytic and synthetic way of learning. Due to the above mentioned facts the tool provides a unique training platform to use in courses on electronic testing and design for testability.

Linear feedback shift registers (LFSR) and other pseudo-random pattern generators (PRPG) have become one of the central elements used in testing and self testing of contemporary complex electronic systems like processors, controllers, and high-performance integrated circuits. The current paper describes a training and research tool for learning basic and advanced issues related to PRPG-based test pattern generation. Unlike other similar systems, this tool facilitates study of various test optimization problems, allows fault coverage analysis for different circuits and with different LFSR parameters. The main didactic aim of the tool is presenting complicated concepts in a comprehensive graphical and analytical way. The multi-platform JAVA runtime environment allows for easy access and usage of the tool both in a classroom and at home. The BIST analyzer represents an integrated simulation, training, and research environment that supports both analytic and synthetic way of learning. Due to the above mentioned facts the tool provides a unique training platform to use in courses on electronic testing and design for testability. The BIST Analyzer has got a positive feedback from students of Darmstadt TU (Germany) and Tallinn TU (Estonia).

Classical built-in self-test (BIST) architectures are usually relying on linear feedback shift registers (LFSR) for test set generation and test response compaction. This paper is based on extension of the classical BIST, namely hybrid BIST, where pseudorandom test patterns are complemented with precomputed deterministic test patterns to increase the fault coverage and reduce test time. We will propose a method, based on store-and-generate approach, to find the optimal balance between pseudorandom and stored deterministic test patterns. The objective is to minimize the test time at given memory constraints, without losing test quality. We propose an iterative search method and the experimental results on benchmark circuits have proved the efficiency of the proposed approach for hybrid BIST optimization.