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International audience; A fully deterministic digital background calibration for pipeline ADCs is presented. The proposed approach is based on split ADC concept to give the shortest background calibration time with high accuracy. A slope mismatch averaging technique is employed in a multistage calibration scheme to deterministically detect the circuit errors without any iterative operations or feedback loops, which render it fast and accurate. Analysis and behavioral simulations for the developed multistage calibration demonstrate the efficiency of this technique and its merit over the LMS-based techniques. Practical considerations have been considered and the proposed calibration has been applied on a 200 MS/s 40 nm CMOS split pipeline ADC to correct for the capacitor mismatch and the amplifier finite gain. The post-layout simulation results show a very fast calibration cycle, where the ADC achieves more than 11 ENOB in less than 1600 clock cycles.

International audience; The goal of this paper is to provide design considerations for the use of low gain amplifier presents in the Multiplying Analog-to-Digital Converter (MDAC) of pipelined ADCs with gain error correction in the digital domain. Using low gain amplifier in the MDAC makes the pipelined ADC more susceptible to gain variation and harmonic distortion, impacting the ADC performance. Theory and simulations are presented to provide design insight into the trade-off between minimum gain and its variations to preserve the calibrated ADC performance. These considerations are demonstrated on the MDAC of a 12 bit digitally calibrated pipelined ADC designed in 40nm CMOS technology.

International audience; A slope mismatch averaging technique which reduces the calibration time and simplifies the digital calibration circuitry in split ADC calibration is introduced. The technique is a direct operation to perform split ADC calibration in pipelined analogue-to-digital converters (ADCs) without any feedback, thus achieving a significant reduction in calibration time.

International audience; A foreground digital calibration technique for pipelined ADC is proposed which accounts for linear error correction, while an error estimation technique for amplifier non-linearity is suggested as a reference for non-linear error correction. The calibration algorithm is based on applying a slow input to the ADC to automatically correct for linear errors, while depending on the accuracy of Digital Error Correction (DEC) to estimate and correct for non-linear errors. The proposed calibration scheme is demonstrated for an 11 bit pipelined ADC, and gives SNDR improvement over 30 dB, while using low specifications residue amplifier to reduce power consumption.