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Springback compensation is considered as the best method to reduce springback error. In view of the springback defect of 3D deformed workpiece, a springback compensation method based on variable compensation factor is proposed. This method can accelerate the convergence speed of iterative compensation. In this paper, the 3D flexible stretch bending of multi-point roller die technology (3D FSB-MPRD) is introduced firstly, and then, the principle of the springback compensation method based on variable compensation factor is explained. In order to improve the springback compensation accuracy of workpiece, the total springback compensation process is divided into horizontal bending springback compensation and vertical bending springback compensation. Taking the T-shaped profile with variable curvature as the research object, the die surface is optimized and the optimal springback compensation factor is obtained by using numerical simulation after multiple iterations. Finally, the results of springback compensation are compared with the desired shape. And the effectiveness of the springback compensation method based on variable compensation factor is verified by comparing the simulation results with the test results.

Resistive random access memory device (RRAM) has been widely used in various novel circuit systems, such as memory, artificial intelligence, and neural networks, due to its unique memory characteristics. However, there are very few studies focusing on analytic modeling of RRAM. In this article, modeling for solving analytic approximate solution to the state variable of RRAM, based on the proposed Multistage Homotopy Analysis Method (MuHAM), is proposed. Different from traditional HAM, the time span under consideration is divided into many subintervals, then the convergence control parameter in each subinterval is optimized to achieve high approximation accuracy. By simulating and comparing the obtained analytic solutions with solutions solved by other traditional homotopy-based modeling methodologies and by numerical analyses, we verified that MuHAM has higher Quality Factor (introduced to evaluate the model accuracy and computational cost comprehensively), hence improving the simulation efficiency. Besides the classical Hewlett-Packard (HP) RRAM, some current RRAMs are also verified. MuHAM also has the advantages of enabling both qualitative and quantitative analyses, and immunity to convergence issues. It is particularly suitable for the analytic modeling of the other novel memory devices having strong nonlinearity.

Memristive nonlinear system has drawn much attention in recent years, due to its rich and complex dynamical characteristics. However, there are few studies focus on the analytical analysis of this significant system. In this paper, a novel analytical method for analyzing the chaotic trajectories of memristive circuit is proposed. This method combines Homotopy Analysis Method (HAM) and Multi-objective Optimization (MO), i.e., the convergence control parameter of traditional HAM is divided into lots of subintervals in the time domain and respectively optimized by MO, for accurately solving the Ordinary Differential Equations describing memristive circuits. Hence, this method is named by MO-based multi-interval HAM (MO-MIHAM). By using MO-MIHAM, we accurately tracked the chaotic trajectories of the classical Memristor-Capacitor-Inductor (MCL) circuit and current memristive Band Pass Filter (BPF) chaotic circuit. Furthermore, based on the comparisons of errors between analytical approximate solutions derived from MO-MIHAM and solutions solved by traditional homotopy-based analytical methods and by Runge-Kutta-Fehlberg Method (RKF45) based numerical analysis, we found that, MO-MIHAM is characterized by higher approximation accuracy and computational performance (comprehensively considering the accuracy, computational complexity and execution time by a proposed Quality Factor) among the homotopy-based analytical methods, due to the optimized convergence control parameters in subintervals. Besides this major advantage, MO-MIHAM enables both qualitative and quantitative analyses and high freedom to choose homotopy-related terms for simplicity, and it is insensitive to convergence issues. Therefore, it is a powerful tool for exploratory studies for analytically analyzing chaotic dynamics in memristive circuit.

Scan testing is the key technology in the design for test of integrated circuit. For existing scan testing methods, the scan-in for test stimuli requires many clock cycles, which is one of the main restrictions of scan testing. To shorten the scan testing time of an integrated circuit, a novel test stimulus scan-in method was proposed in this study. First, scan chains, test stimuli, and test responses were grouped according to a fixed data width. Second, logic XOR calculation results of test response and test stimuli were coded according to the bit width of each group. The corresponding decoding and control circuits were added in the netlist of the circuit, which achieved fast input of test stimuli. Finally, an experiment using ISCA89 and IWLS2005 benchmark test circuits was performed. Experimental results were compared with those that used a serial input method of test stimuli. Results demonstrate that the proposed method can save approximately 37.5% and 43.7% of test time in average when the width of each group are 4 bits and 8 bits, respectively. The proposed method can decrease the clock cycles of scan testing significantly and shorten the scan testing time of the integrated circuit. Conclusions obtained in this study provide significant references for improving the scan testing method of digital integrated circuit. Keywords: Scan testing, Design for test, Test response, Test stimulus

Special accelerator architecture has achieved great success in processor architecture, and it is trending in computer architecture development. However, as the memory access pattern of an accelerator is relatively complicated, the memory access performance is relatively poor, limiting the overall performance improvement of hardware accelerators. Moreover, memory controllers for hardware accelerators have been scarcely researched. We consider that a special accelerator memory controller is essential for improving the memory access performance. To this end, we propose a dynamic random access memory (DRAM) memory controller called NNAMC for neural network accelerators, which monitors the memory access stream of an accelerator and transfers it to the optimal address mapping scheme bank based on the memory access characteristics. NNAMC includes a stream access prediction unit (SAPU) that analyzes the type of data stream accessed by the accelerator via hardware, and designs the address mapping for different banks using a bank partitioning model (BPM). The image mapping method and hardware architecture were analyzed in a practical neural network accelerator. In the experiment, NNAMC achieved significantly lower access latency of the hardware accelerator than the competing address mapping schemes, increased the row buffer hit ratio by 13.68% on average (up to 26.17%), reduced the system access latency by 26.3% on average (up to 37.68%), and lowered the hardware cost. In addition, we also confirmed that NNAMC efficiently adapted to different network parameters.

Timing optimization for logic circuits is one of the key steps in logic synthesis. Extant research data are mainly proposed based on various intelligence algorithms. Hence, they are neither comparable with timing optimization data collected by the mainstream electronic design automation (EDA) tool nor able to verify the superiority of intelligence algorithms to the EDA tool in terms of optimization ability. To address these shortcomings, a novel verification method is proposed in this study. First, a discrete particle swarm optimization (DPSO) algorithm was applied to optimize the timing of the mixed polarity Reed-Muller (MPRM) logic circuit. Second, the Design Compiler (DC) algorithm was used to optimize the timing of the same MPRM logic circuit through special settings and constraints. Finally, the timing optimization results of the two algorithms were compared based on MCNC benchmark circuits. The timing optimization results obtained using DPSO are compared with those obtained from DC, and DPSO demonstrates an average reduction of 9.7% in the timing delays of critical paths for a number of MCNC benchmark circuits. The proposed verification method directly ascertains whether the intelligence algorithm has a better timing optimization ability than DC.

High precision and smart sensors make up an indispensable data entry for the Internet of Things technology. Nonetheless, conventional calibration algorithms mainly implemented on the software, such as least squares, polynomial fitting, and interpolation, exhibit limited calibration accuracy that does not reflect a real-time measurement of the sensors. The problem can be resolved with an MCU-based sensor calibration system proposed herein, which mainly employs particle swarm optimization (PSO)-back propagation (BP) neural network. The system firstly reads sensor data through I2C bus and then uses the BP neural network and PSO algorithm to automatically calibrate these data in real time. Sigmoid activation function was implemented via a piecewise polynomial fitting to create a trade-off between hardware resource and precision. A performance test conducted on temperature sensors showed a maximum error of 0.16 °C within the measurement range of −40–100 °C with three times the standard deviation (3 σ ) error of ±0.23 °C and overall linearity of 0.1143% after the calibration system was added as compared to the significantly higher error of ±0.63 °C without the calibration.

A CCD control system based on dsPIC Digital Signal Controller(DSC) which integrates two ADC modules is designed. As a result, the DSC device simplifies the circuit arrangement, reduces the cost and improves the compatibility of the CCD control system. CCD Work timing and ADC work timing are emphasized. The experimental results show the simplification and practicality through application of this CCD control system.