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Where the number of new student registrants at the Sinar Harapan Private Vocational School is unstable every year and the school has difficulty predicting how many new student registrants will be in the coming year and preparing extracurricular activities such as English/computer training or the best facilities for new students such as chairs, tables, classrooms and so on, as well as the competitiveness of private schools in the district. banyan. So we need a system that can dig up data and help predict the number of new student registrants, using data mining techniques, namely the Rough Set Algorithm which aims to get a short rule estimate from a table, in this study using student registration data in 2018, 2019, 2020. By applying data mining with the rough set algorithm and carrying out the rough set stages, it can produce decisions in the form of generating rules (knowledge), and the results of the calculation analysis are 152 students to predict the number of students in the coming year.

The blocking performance of extended pruned vertically stacked optical banyan (VSOB) networks under different link failure conditions has been analyzed in this paper. We applied plane fixed routing with linear search and plane fixed routing with random search algorithms to route the optical data through the network in our simulation. Our simulation results show that adding one or two extra planes to the pruned VSOB network reduces the blocking probability significantly. Beyond two extra planes, the decrease of blocking probability is not so significant. A close approximation of the minimum number of planes required to make the extended pruned vertically stacked optical banyan networks nonblocking has been presented.

The paper shows the possibility to reduce energy consumption in banyan-type switching fabrics working under different control algorithms. This can be done by adopting the structure of switching fabric to the intensity of traffic offered, providing lossless operation of the switching fabric at the same time. An analytical model determining the number of planes which is required for lossless servicing the offered traffic is also presented. Results obtained from the model are compared with simulation result showing high accuracy of the proposed model. The paper demonstrates also that, when using the proposed model, the amount of saved electrical energy, consumed by a switching fabric composed of switching elements based on Mach-Zhander interferometers, starts from a few watts (for switching fabric with 64 inputs) up to 1 kW (for switching fabric with 1024 inputs).

The article discusses the strict-sense nonblocking conditions derived for thelog2⁡N-1multirate switching fabric for the discrete bandwidth model at the connection level. Architecture of thelog2⁡N-1switching fabric was described in previous study; however, conditions for the multirate discrete bandwidth model as well as comparison with different structures have not been published before. Both sufficient and necessary conditions were introduced and proved in this study. A few numerical examples which help to understand an idea of the multirate bandwidth model for thelog2⁡N-1switching fabrics were delivered as well. Additionally a comparison of achieved results to thebanyanswitching structures and a comparison of the costs of all mentioned in this study structures expressed as the number of optical elements were done.

Logic locking is a method to prevent intellectual property (IP) piracy. However, under a reasonable attack model, SAT-based methods have proven to be powerful in obtaining the secret key. In response, many locking techniques have been developed to specifically resist this form of attack. In this paper, we demonstrate two SAT modeling techniques that can provide many orders of magnitude speed up in discovering the correct key. Specifically, we consider relaxed encodings and symmetry breaking. To demonstrate their impact, we model and attack a state-of-the-art logic locking technique, Full-Lock. We show that circuits previously unbreakable within 15 days of run time can be solved in seconds. Consequently, in assessing the strength of any given locking, it is imperative that these modeling techniques be considered. To remedy this vulnerability in the considered locking technique, we demonstrate an extended version, logic-enhanced Banyan locking, that is resistant to our proposed modeling techniques.

Programming loosely connected distributed applications is a challenging endeavour. Loosely connected distributed applications such as geo-distributed stores and intermittently reachable IoT devices cannot afford to coordinate among all of the replicas in order to ensure data consistency due to prohibitive latency costs and the impossibility of coordination if availability is to be ensured. Thus, the state of the replicas evolves independently, making it difficult to develop correct applications. Existing solutions to this problem limit the data types that can be used in these applications, which neither offer the ability to compose them to construct more complex data types nor offer transactions.

Banyan network is a multistage communication architecture that route the input signal based on port address of receiver. The port address is recognized as a string. This paper illustrates the design of a novel single layer banyan network using QCA for nanocommunication. To design the proposed communication architecture, a new single layer 2-inputs and 2-outputs crossbar switch is proposed and implemented in QCA. Using this crossbar switch as a major building block, a 4x4, and 8x8 banyan networks have been achieved in this paper. The effect of stuck-at-fault at the control input is observed and excelled for fault free design of the crossbar switch. Similarly, the fault tolerant nature of the proposed banyan networks have been characterized by considering the stuck-at-fault effect at the control signals of crossbar switches within the architecture. The designs are evaluated considering device area, delay, and logic gates. Theoretical values have been matched up with the simulation results to verify design accuracy.

Utilization of information technology and computer network as data communication media has been increased. The requirement for shared use of existing resources in the network both software and hardware has resulted in the development of various technologies of the network itself. Information technology and communications are widely used today using computer network system as a medium of information and data transformation, the greater the company or agency that uses the network computer the more complex the network system in the company or agency, and required a good handling for the system can run optimally. One of them that uses computer network system is Banyan Tree Bintan. Network monitoring activities in Banyan Tree Bintan are important to do by network administrator to ensure the network is always in good condition. Given the limitations of network administrators who can not always be in the workplace, it is necessary for a system that can monitor the computer network remotely. So that the network administrator can know the state of the computer network at any time and can perform actions that need to be done quickly.This application is based on android using an Internet connection for network administrators can monitor network anytime and anywhere. Desktop-based applications need to be installed on the computer so that computer system data can be retrieved and displayed on android devices.

Highly fault-tolerant optical switch is becoming a critical network element for large wavelength division multiplexing mesh networks. Optical nodes built on replicated banyan network (RBN) structures are attractive for serving as optical switching systems due to the nice properties of banyan network structures. Furthermore it is expected that an optical RBN structure also has a good fault-tolerant capability because it consists of multiple identical banyan networks. Previous analytical models have been developed to understand the blocking behaviors of optical RBN networks without taking into account the link failure in optical RBN networks. In this paper, we conduct the link failure-tolerant analysis of optical RBN networks and present an analytical model for the blocking probability of optical RBN networks when link failures are taken into account. The model is significant because it provides network developers a quantitative guidance to determine the effects of network failure on the overall blocking behaviors of optical RBN networks and enables a desirable tradeoff to be made between blocking probability and hardware cost in a faulty optical RBN network.

Banyan networks serve as a class of important switching network architecture, whose multicast capability is critical for future high-performance switches to support multicast-intensive applications. The available literature indicates that, in order to construct optical multicast banyan networks based on the directional coupler (DC) technology, a high-hardware cost is usually involved to ensure the nonblocking property. In this paper, we conduct blocking probability analysis for such networks to explore the inherent tradeoff between blocking probability and hardware cost. In particular, we focus on a class of DC-based optical networks built on the replicated banyan network (RBN) architecture, and develop a theoretical upper bound on blocking probability for such networks under the general $f$ -cast traffic, which covers the unicast and multicast as special cases. This bound captures the overall blocking behavior of $f$ -cast optical RBN networks and agrees with the conditions of strictly nonblocking $f$ -cast optical RBN networks. The proposed bound is significant because it provides a fundamental guideline to achieve the desirable tradeoff between blocking probability and hardware cost. This paper shows that the hardware cost of an $f$ -cast optical RBN network can be dramatically reduced if a small blocking probability is allowed.

Multistage switching is generally built by using crossbar switches in according to Clos architecture which has small blocking probabilities. However, number of cross points increases significantly to numbers of input output. This paper analyses the implementation of Batcher Banyan configuration to multistage switching system to reduce number of cross points. As Batcher Banyan sorts input to output ports, besides reducing cross points, it avoids collision among its input output. The Clos crossbar multistage switching requires up to 1,560,576 cross points with 6.9x10-17 blocking probability, but Batcher Banyan needs only 294,912 cross points, 429.17% lower, with zero blocking probability for the same numbers of input output.

Switching units and networks have been analyzed as extensible fabrics, mostly in terms of their scheduling algorithms. The traditional literature on switching extensibility has provided complexity theory only relating to the total numbers of inputs (or outputs) and exchange lines. This paper analyzes switching extensibility in terms of not only the scheduling algorithm and also the fabric itself. It is found that determining extensibility from soft complexity related to the number of inputs (or outputs) of the scheduling algorithm and the fabric extensibility in previous studies without quantization is a flawed conception. A method is thus proposed to express the spatial extensibility of a switching unit or network in terms of the connections of a switching resource and capacity. The method calculates parameter ES (the efficiency of switching) of an m× n switching unit and obtains two functions of the switching unit to describe spatial extensibility along with the number of unilateral inputs or outputs. It is found that the range of ES is (0, 1] and three types of switching unit and two types of crosspoint networks have ES = 1. ES is calculated for banyan, Clos, parallel packet, fully interconnected and recirculation switching networks. The ES value for the banyan switching network is larger than that for other networks, and switching networks are classified into three types that have absolute/linear/denied spatial extensibility according to the limES value. It is demonstrated that a switching network has the largest ES value when it contains only the five types of switching unit for which ES = 1. Finally, a group-switching-first self-routing banyan switching network with lower blocking probability and time delay is deduced, and the ES method is contrasted with two other methods of evaluating spatial extensibility in terms of their mathematical expressions and intuitive graphics, for the five types of switching network listed above.

Fault tolerance and energy consumption are two key aspects of future Network-on-Chips (NoCs). The utilization of deflection routing and Banyan networks for fault-tolerant and energy efficient router architectures was proposed recently. Compared to traditionally deployed crossbars, Banyan networks can reduce hardware costs and improve the energy efficiency of router architectures. However, they also cause substantial disadvantages in terms of fault tolerance, as they are internal blocking, single-path networks. In contrast, Benes networks have some considerable advantages if they are used for fault-tolerant NoCs, as they are rearrangeable non-blocking, multi-path networks. In this paper, we identify the problems of Banyan networks when it comes to fault tolerance. Further, we show that a router architecture, which is instead based on a Benes network, can solve all identified problems, if constructed carefully. Comparisons to existing fault-tolerant and deflection routing based NoCs are presented. The achieved results show, that compared to Banyan networks, Benes networks can improve the performance at almost no additional hardware costs.

This paper introduces with the selector-tree network a new self-routing and non-blocking interconnection network: The n × n network is capable of routing any permutation of its n inputs to its n output ports and is therefore non-blocking, and thus, more powerful than Ω-permutation and Banyan networks. In contrast to other non-blocking interconnection networks like the Benes network, our selector-tree network does not need an additional setup time since the target addresses of the connections directly define the conflict-free routes so that the network is self-routing. The overall depth of the network depends on the implementation of its building block, the selector module: In this paper, we present two preliminary alternatives where the more expensive one requires O(log(n)2) time and O(n2 log(n)) gates while the other one requires O(n) cycles and only O(n) gates for the n × n network. The two alternatives can also be combined to optimize both time and size for particular sizes.

With the growing of cloud computing, the need of computing power no longer can be satisfied with a few powerful servers or small scale parallel computer systems. More and more servers are connected together as a data center network. Then, fault tolerance becomes an import issue when building a massive data center network. Currently, many researches focus on building fat-tree data center networks. In this paper, we propose a load balanced fat-tree architecture with uniform mapping connection patterns to provide higher fault tolerance capability for heavy traffic load networks. Two fault tolerated 4 ? 4 banyan type switch designs are introduced to improve the fault tolerance capability of fat-tree networks. Finally, fault tolerance capability evaluations of link or switch faults in fat-tree network are given to support our idea, and a 4 ? 4 banyan type switch IC is demonstrated as the commodity switch for building the fault tolerant fat-tree data center networks. The 4 ? 4 banyan type switch IC is fabricated in 90 nm CMOS technology, and the maximum operation rate of the IC is 5.8 Gbps per channel or 23.2 Gbps total data rate with only 23 ps peak-to-peak jitter.

Multistage interconnection networks (MINs) are a basic class of switch-based network architectures, which are used for constructing scalable parallel computers or for connecting networks. Semi-layer MINs are a special case of MINs. A performance evaluation of semi-layer MINs (using simulation models) is presented in this paper. The configurations of the under study networks apply a conflict drop resolution mechanism. The proposed architecture's performance is studied under uniform traffic conditions and various offered loads, buffer-lengths and MIN sizes. In this paper, the improvements on semi-layer MIN performance, in terms of throughput and latency, are demonstrated quantitatively. These performance measures can be valuable tools for designers of parallel multiprocessor systems and networks, in order to minimize the overall deployment costs and help deliver efficient systems.

Low-Density Parity-Check codes are one of the best modern error-correcting codes due to their excellent error-correcting performance and highly parallel decoding scheme. This article concerns the hardware iterative decoder for a subclass of LDPC codes that are implementation oriented, known also as Architecture Aware LDPC. The parameterizable decoder has been designed in the form of synthesizable VHDL description. Implementation in Xilinx FPGA devices achieves throughput nearly 100Mb/s. Significant part of the decoder area is occupied by Configurable Interconnection Network. The network consists of a set of multiplexers that propagate the data from memory to the computation units. Behavioral description of the interconnection network gives quite poor synthesis results: decoder area is large and exponentially dependent on the number of inputs / outputs. Instead of straightforward behavioral description, the switching network can be described structurally making use of ideas known from theory of telecommunication interconnection networks: Benes or Banyan switches. In this article 1 present in detail the interconnection network implementation based on Banyan switch with additional multiplexer stage to enable non-power-of-2 numbers of outputs. Comparison of synthesis results for the network obtained by synthesis of behavioral description as well as the Banyan structural description shows significant decrease of decoder area in the second case.

We introduce here a designing of 2x2 MZI (Mach-Zehnder Interferometer) optical switch. The switching of the optical signal is realized with the use of fast electro-optical effects. The designed model has a very high switching capability and is extremely reliable. Various design parameters have been varied to improve the performance of the switch. Then the basic 2×2 switch is exploited in design of 4×4 banyan switch. Banyan switch is a good candidate for further use in higher order switches. Simulation results are shown for 2×2 and 4×4 banyan architecture with low cross-talk values.

Vertically stacked pruned optical banyan networks with extra planes (in short, EP-VSOB networks) have lower switch count and optimal time complexity (O(log2 N)) for routing N input requests. However, blocking probability is relatively higher than that of a VSOB networks using regular banyan planes. In the EP-VSOB architecture, the number of pruned planes has always been considered as N , and a few extra planes (regular banyan) have been added with these pruned planes. In this paper we present the results of blocking analysis of a more generalized architecture in which the number of pruned planes can be 2x, where x ⩾ 0 in addition to the variable extra planes. This generalization helps us make a compromise between different constraints and performance metrics. Our simulation results show that for some given performance requirements (e.g. cost, speed or blocking probability) we can choose a network that has lower switch count compared to N -plane pruned crosstalk-free optical banyan networks. For example, to ensure blocking probability

The banyan network plays an important role in optical interconnection networks. A smart and compact double banyan network with cascading banyan network and inverse banyan network is proposed by using a polarizing beam-splitter (PBS), a phase spatial light modulator (PSLM), a half-wave plate (HWP), a double-faced reflective mirror (DFRM), and mirrors. The PBS features that the s-component (perpendicular to the incident plane) of the incident light beam is reflected, and the p-component (parallel to the incident plane) passes through it. Simultaneously, the bipartition graph algorithm (BGA) is adopted to ascertain the state of the node switch in each node stage (straight or crossover connection). According to switching logic, under control of external electrical signals, the PSLM functions to control routing paths of the signal beams, i.e. the polarization of each optical signal is rotated or not rotated 90° by a programmable PSLM. Since the proposed optical setup consists of only optical polarization eleme...

Vertically stacked optical banyan (VSOB) is an attractive architecture for constructing banyan-based optical switches. Blocking behaviors analysis is an effective approach to studying network performance and finding a graceful compromise among hardware costs, blocking probability and crosstalk tolerance; however, little has been done on analyzing the blocking behavior of VSOB networks under crosstalk constraint which adds a new dimension to the switching performance. In this paper, we study the overall blocking behavior of a VSOB network under various degree of crosstalk, where an upper bound on the blocking probability of the network is developed. The upper bound depicts accurately the overall blocking behavior of a VSOB network as verified by extensive simulation results and it agrees with the strictly nonblocking condition of the network. The derived upper bound is significant because it reveals the inherent relationship between blocking probability and network hardware cost, by which a desirable tradeoff can be made between them under various degree of crosstalk constraint. Also, the upper bound shows how crosstalk adds a new dimension to the theory of switching systems.

A new control algorithm for log2(N, 0, p) switching networks composed of 2 x 2 switching elements has been proposed recently. Under this algorithm, log2(N,0,p) switching networks with even number of stages are wide-sense nonblocking (WSNB) if p is the same as for the rearrangeable nonblocking (RNB) one. The considerred algorithm and WSNB conditions did not take into account crosstalk constraint, which is an important factor in photonic switching. This paper enhanced this algorithm to the case when crosstalk in the switching fabric is not allowed. WSNB conditions for this enhanced algorithm are also derived. It is shown, that the number of planes required is less than those derived earlier in other papers for WSNB multiplane banyan- type switching fabrics under crosstalk constraint. Under this algorithm, log2( N,0,p) switching networks with odd number of stages and with zero crosstalk are WSNB if p is the same as for RNB one.

CC-Banyan network plays an important role in the optical interconnection network. Based on previous reports of (2, 2, 3) the CC-Banyan network, another rectangular-Banyan network, i.e. (3, 3, 2) rectangular CC-Banyan network, has been discussed. First, according to its construction principle, the topological graph and the routing rule of (3, 3, 2) rectangular CC-Banyan network have been proposed. Then, the optically experimental setup of (3, 3, 2) rectangular CC-Banyan network has been designed and achieved. Each stage of node switch consists of phase spatial light modulator (PSLM) and polarizing beam-splitter (PBS), and fiber has been used to perform connection between adjacent stages. PBS features that s-component (perpendicular to the incident plane) of the incident light beam is reflected, and p-component (parallel to the incident plane) passes through it. According to switching logic, under the control of external electrical signals, PSLM functions to control routing paths of the signal beams, i.e. the polarization of each optical signal is rotated or not rotated 90° by a programmable PSLM. Finally, the discussion and analysis show that the experimental setup designed here can realize many functions such as optical signal switch and permutation. It has advantages of large number of input/output-ports, compact in structure, and low energy loss. Hence, the experimental setup can be used in optical communication and optical information processing.

All-to-all personalized exchange occurs in many important applications in parallel processing. In the past two decades, algorithms for all-to-all personalized exchange were mainly proposed for hypercubes, meshes, and tori. Recently, Yang and Wang (IEEE Trans Parallel Distrib Syst 11:261–274, 2000) proposed an optimal all-to-all personalized exchange algorithm for binary (each switch is of size 2×2) banyan multistage interconnection networks. It was pointed out in Massini (Discret Appl Math 128:435–446, 2003) that the algorithm in Yang, Wang (IEEE Trans Parallel Distrib Syst 11:261–274, 2000) depends on the network topologies and requires pre-computation and memory allocation for a Latin square. Thus in (Discret Appl Math 128:435–446, 2003), Massini proposed a new optimal algorithm, which is independent of the network topologies and does not require pre-computation or memory allocation for a Latin square. Unfortunately, Massini’s algorithm has a flaw and does not realize all-to-all personalized exchange. In this paper, we will correct the flaw and generalize Massini’s algorithm to be applicable to d-nary (each switch is of size d×d) banyan multistage interconnection networks.

The cascade of two baseline networks in tandem is a rearrangeable network. The cascade of two omega networks appended with a certain interconnection pattern is also rearrangeable. These belong to the general problem: for what banyan-type network (i.e., bit-permuting unique-routing network) is the tandem cascade a rearrangeable network? We relate the problem to the trace and guide of banyan-type networks. Let τ denote the trace permutation of a 2n × 2n banyan-type network and γ the guide permutation of it. This paper proves that rearrangeability of the tandem cascade of the network is solely determined by the transposition τγ-1. Such a permutation is said to be tandem rearrangeable when the tandem cascade is indeed rearrangeable. We identify a few tandem rearrangeable permutations, each implying the rearrangeability of the tandem cascade of a wide class of banyan-type networks.

The feedback-based switch [1] is a load-balanced switch consisting of two stages of crossbar switch fabrics. Each crossbar switch fabric is configured according to a predetermined and periodic seuqence of switch configurations. This eliminates the need for a central scheduler and makes it an excellent candidate for connecting tens of thousands of servers in a data center. But implementing feedback-based switch at the data center scale is challenging. A major issue is that crossbar switch fabrics are not scalable. In this paper, two scalable implementations of the feedback-based switch, dualbanyan network and Clos-banyan network, are proposed. With the dual-banyan implementation, the two crossbar switch fabrics are replaced by two modular banyan networks. To further reduce the dual-banyan network complexity, we merge the last stage of switch modules in the first banyan, the middle-stage ports, and the first stage of switch modules in the second banyan, to form a single stage of shared-memory switch modules. We call the resulting network Clos-banyan. We prove that the feedback-based switch implemented using either dual-banyan or Clos-banyan can realize all the switch configurations required by the original crossbarbased implementation, but at a much lower hardware cost. Since the packet scheduling algorithm is independent of how switch configurations are being realized, different implementations of the feedback-based switch provide the same excellent delaythroughput performance, as that already reported in [1].

Nowadays, network management has become difficult because of tremendous increase on IP traffic demands. At this point, a flexible and dynamic control mechanism is needed that diminishes the complexity of physical topology. Software Defined Networking (SDN), is one of the proposed next generation technologies to overcome this problem. SDN paradigm provides a simple management strategy for dummy switches in physical topology by moving their control logic to Control Plane. However, on one hand, network management becomes more scalable and flexible with this technology; on the other hand, there is an extra delay caused by OpenFlow switch architecture that should not be regarded according to Quality of Service (QoS) of a flow. This delay is arised from matching many header fields for many times while forwarding a flow in OpenFlow switch table pipeline. Therefore, we propose a novel OpenFlow switch architecture to lower temporal complexity by using Banyan Network model. The proposed model is able to forward a flow by less header matching and also protect dummy characteristic with an additional field called next table identifier. Flow forwarding in each pipeline of Banyan Network model is performed according to this next table identifier. Moreover, the advantages of Network on Chip (NOC) are also applied to OpenFlow forwarding mechanism by assigning a microcontroller to each flow table in each pipeline. Consequently, thanks to many pipelines that can serve the flows in parallel, the number of flows that are served per unit time is increased and the QoS of each flow is enhanced.

We consider a problem motivated by the desire to provide flexible, rate-based, quality of service guarantees for packets sent over input queued switches and switch networks. Our focus is solving a type of online traffic scheduling problem, whose input at each time step is a set of desired traffic rates through the switch network. These traffic rates in general cannot be exactly achieved since they assume arbitrarily small fractions of packets can be transmitted at each time step. The goal of the traffic scheduling problem is to closely approximate the given sequence of traffic rates by a sequence of transmissions in which only whole packets are sent. We prove worst-case bounds on the additional buffer use, which we call backlog, that results from using such an approximation. We first consider the NtimesN, input queued, crossbar switch. Our main result is an online packet-scheduling algorithm using no speedup that guarantees backlog at most (N+1)2 /4 packets at each input port and each output port. Upper bounds on worst-case backlog have been proved for the case of constant fluid schedules, such as the N2-2N+2 bound of Chang, Chen, and Huang (INFOCOM, 2000). Our main result for the crossbar switch is the first, to our knowledge, to bound backlog in terms of switch size N for arbitrary, time-varying fluid schedules, without using speedup. Our main result for Banyan networks is an exact characterization of the speedup required to maintain bounded backlog, in terms of polytopes derived from the network topology

Banyan networks are attractive for serving as the optical switch architectures due to their nice properties of small depth and absolutely signal loss uniformity. Combining the horizontal expansion and vertical stacking of optical banyan networks is a general scheme for constructing banyan-based optical switching networks. The resulting horizontally expanded and vertically stacked optical banyan (HVOB) networks usually take either a high hardware cost or a large network depth to guarantee the nonblocking property. Blocking behavior analysis is an effective approach to studying network performance and finding a graceful compromise among hardware cost, network depth, and blocking probability; however, little has been done to analyze the blocking behavior of general HVOB networks. In this paper, we study the overall blocking behavior of general HVOB networks, where an upper bound on the blocking probability of a HVOB network is developed with respect to the number of planes (stacked copies) and the number of stages. The upper bound accurately depicts the overall blocking behavior of a HVOB network as verified by an extensive simulation study, and it agrees with the strictly nonblocking condition of the network. The derived upper bound is significant because it reveals the inherent relationship among blocking probability, network depth, and network hardware cost, so that a desirable tradeoff can be made among them. In particular, our bound gives network developers an effective tool to estimate the maximum blocking probability of a HVOB network, in which different routing strategies can be applied with a guaranteed performance in terms of blocking probability, hardware cost and network depth. Our upper bound model predicts some unobvious qualitative behaviors of HVOB networks, and it draws an important conclusion that a very low blocking probability (e.g., less than 0.001 percent) can be achieved in a HVOB network without introducing either a significantly high hardware cost or a large network depth

In this paper, we address the issue of faster connection establishment in a large vertically stacked optical Banyan (VSOB) network. The best known global routing algorithm, which turns an N × N crosstalk-free VSOB network into a rearrangeably non-blocking one, has time complexity O ( N log N ). This is quite large compared to O ( N log N ) time complexity of a single plane banyan network, which is a self-routing network with very high blocking probability. For a large size of switching network this O ( N log N ) time complexity may result unacceptably long delay. Therefore, an optical network with very low blocking probability and O ( N log N ) time complexity will be useful. Previously proposed Plane Fixed Routing (PFR) algorithm has O (log N ) time complexity but results in higher than 2% blocking probability with zero-crosstalk constraint for a network as large as 4096 × 4096 at full load. In this paper, first we propose the pruning of VSOB networks that reduces the hardware cost by almost 30%. The networks can still use the PFR algorithm and results in the same blocking probability. However, we show that the blocking probability can be reduced dramatically while keeping the optimum time complexity O (log N ) by allowing only a small amount of crosstalk. Then, we propose a new kind of switching networks in which extra regular banyan planes have been added with the pruned VBOS (P-VSOB) networks. Necessary routing algorithms, namely, PFR_RS and PFR_LS show that this new switching network can reduce the blocking probability to very low value even with zero-crosstalk constraint while keeping the hardware cost 3almost the same as for P-VSOB networks. Both these algorithms also have time complexity O ( N log N ).

A combination of horizontal expansion and vertical stacking of optical Banyan (HVOB) is the general architecture for building Banyan-based optical cross-connects (OXCs), and the intrinsic crosstalk problem of optical signals is a major constraint in designing OXCs. In this paper, we analyze the blocking behavior of HVOB networks and develop the lower bound on blocking probability of a HVOB network that is free of first-order crosstalk in switching elements. The proposed lower-bound is significant because it provides network designers an effective tool to estimate the minimum blocking probability they can expect from a HVOB architecture regardless what kind of routing strategy to be adopted. Our lower bound can accurately depict the overall blocking behavior in terms of the minimum blocking probability in a HVOB network, as verified by extensive simulation based on a network simulator with both random routing and packing routing strategies. Surprisingly, the simulated and theoretical results show that our lower bound can be used to efficiently estimate the blocking probability of HVOB networks applying packing strategy. Thus, our analytical model can guide network designers to find the tradeoff among the number of planes (stacked copies), the number of SEs, the number of stages and blocking probability in a HVOB network applying packing strategy.

Vertical stacking is a novel technique for creating nonblocking (crosstalk-free) optical multistage interconnection networks (MINs). In this paper, we propose a new class of optical MINs, the vertically stacked Benes (VSB) networks, for crosstalk-free realization of permutations in a single pass. An N x N VSB network requires at most O(N log N) switching elements, which is the same as the Benes network, and much lower overall hardware cost than that of the existing optical MINs built on the combination of horizontal expansion and vertical stacking of banyan networks, to provide the same crosstalk-free permutation capability. Furthermore, the structure of VSB networks provides a more flexible way for constructing optical MINs because they give more choices in terms of the number of stages used in an optical MIN. We also present efficient algorithms to realize crosstalk-free permutations in an N x N VSB network in time O(N log N), which matches the same bound as required by the reported schemes.

This paper makes a specific proposal regarding the structure of idioms as they are listed in the lexicon, which has important ramifications. Specifically, I suggest that first Merge as well as internal Merge can target subconstituents of structures already built by Merge. This creates structures which I call Banyan trees, in which there is more than one undominated node. I suggest that this model, together with certain assumptions about phases and about the functional sequence of syntactic heads, derive important facts about the structure of idioms.

The scheme of vertical stacking has caught much interest in the design of ultra high-speed communication switches for the past a few years. In particular, the scheme can greatly facilitate the effort of constructing all-optical photonic switches in the event that a banyan network structure is adopted. A vertically stacked photonic banyan (VSPB) network can preserve the good properties of the banyan network structures, such as the small depth and absolute loss uniformity; on the other hand, it introduces a significant increase in the hardware cost. Extensive research efforts have been addressed in determining the minimum number of stacked copies (planes) required for a nonblocking VSPB network. However, very few of them focused on the performance of the VSPB networks in terms of blocking probability. Therefore, in this paper, we study the blocking behavior of the VSPB networks and propose a corresponding analytical model under the random routing strategy. The proposed analytical model is designed to fully explore the property of symmetry in banyan network structures, and can calculate the blocking probability of a VSPB network stage by stage in a recursive manner such that the combinatorial explosion problem is avoided. To verify the proposed model, we conduct extensive simulations, in which the results indicate that our model can accurately describe the blocking behavior of VSPB networks under the random routing strategy and it agrees with the conditions of strictly nonblocking VSPB networks. We find that the proposed analytical model can deeply investigate into the inherent relationship between blocking probability and network hardware cost in terms of the number of planes; as a result, a quantitative guidance for initiating a graceful compromise between blocking probability and hardware cost can be developed based on the analytical model. Our analysis results also show that the hardware cost of a VSPB network can be dramatically reduced by simply allowing a negligible nonzero blocking probability in most of the practical cases. This fact will solidly contribute to the network switch architecture design and enable more practical applications of VSPB networks.

Multistage Interconnection Networks(MINs) have a number of applications in the areas of computer and communications. The most widely researched structure among MIN's is the (1)banyan type network. It has several variations such as buffered banyan, batcher-banyan, tandem banyan, recirculating banyan and banyan with contention resolution phase. Analytical performance evaluation is crucial for justifying the merit of the design in different operational conditions. While several analytical models have been proposed for the performance evaluation of MINs, they are mainly for uniform traffics. Even the models for nonuniform traffics have several shortcomings such as they only consider output buffered structure or do not consider blocking conditions. In this paper, the more accurate models than any other ones so far have been proposed for the performance evaluation of multibuffered banyan-type MIN's under nonuniform traffic condition is obtained. The accuracy of proposed models are conformed by comparing with the results from simulation. Firstly, single buffer model is developed. Markov chain is used for the analysis. Multibuffer model is obtained from single buffer model. Simulation is performed using Discrete Evenet Simulaton(DES) method. As a results, proposed model proves to be very accurate.

Optical interconnection networks suffer from the intrinsic crosstalk problem that should be overcome to make them work properly. Vertical stacking of optical banyan networks is a novel scheme for constructing nonblocking optical multistage interconnection networks (MINs). Rearrangeable nonblocking optical MINs are feasible since they have lower complexity than their strictly nonblocking counterparts. In this paper, we determine the sufficient condition for these MINs to be rearrangeable nonblocking under various crosstalk constraints. We show how the crosstalk constraint affects the design of rearrangeable nonblocking MINs and demonstrate that these networks can tolerate a stricter crosstalk constraint without increasing their hardware complexity significantly. The results in the paper will be useful in designing optical MINs with reasonable hardware cost and crosstalk level.

The constant advances in IC technologies have introduced new challenges for implementations and design methodologies; higher integration level allows more complex systems to be implemented but on the other hand implementations often have strict constraints on power consumption. These challenges are present in signal processing systems implying the need to improve design methods and find more efficient algorithm-architecture optimizations. This special issue contains a selection of recent papers on design and implementation of signal processing systems ranging from circuit level architectures to scheduling methods and from application-specific architectures to implementations on many-core systems. In Data Center Switch for Load Balanced Fat-Trees, Lai, and Chiu demonstrate a fault tolerant switch IC operating at the maximum rate of 5.8 Gbps per channel. This work employs a load-balanced fat-tree architecture that does not consume all of its bandwidth even under heavy traffic. When there are broken links or faulty switches in the network even in heavy traffic load situations, available bandwidth remains in every connection pattern and alternative paths are provided to re-route the traffic. Fault tolerance capability evaluations of link or switch faults in the fattree network are given to support the presented idea, and a 4×4 Banyan type switch IC is developed as the commodity switch for building the fault tolerant fat-tree data center networks. Lee and Sung propose a cell-to-cell interference (CCI) cancellation technique for multi-level NAND flash memory in their paper Least Squares Based Coupling Cancellation for MLC NAND Flash Memory with a Small Number of Voltage Sensing Operations. Their two-step algorithm consists of training and then interference removal performed during the page read operation. A least-squares adaptive CCI canceller is developed and optimal quantization schemes are studied. Experimental results show a significant BER improvement despite a low number of voltage sensing operations. In A Fast Recursive Algorithm and Architecture for Pruned Bit-Reversal Interleavers, Mansour describes an algorithm and architecture for implementing interleavers used in communications applications such as errorcorrecting codes (turbo codes) and bit-interleaved coded modulation. A mathematical formulation for developing flexible-length interleavers is developed along with a study of permutation statistics. Practical examples of implementations of parallel interleavers are provided. In Highly Parallelable Bidimensional Median Filter for Modern Parallel Programming Models, Sanchez and Rodriguez present efficient parallel implementation methods for median filtering. The authors implement their previous work on the parallel ccdf-based median filter (PCMF) on a GPU (Graphics Processing Unit), and show that the proposed median filtering algorithm is efficient and can outperform other generic median filters for the GPU. The proposed algorithm is implemented in three parallel programming models: SIMD Intel, multi-core Intel with SIMD, and SIMT (CUDA). Additionally they make use of the salt & pepper noise model to improve the image reconstruction quality with a small performance impact. J. Takala (*) Department of Pervasive Computing, Tampere University of Technology, Tampere, Finland e-mail: jarmo.takala@tut.fi

Vertical stacking of multiple optical banyan networks is a novel scheme for building banyan-based nonblocking optical switches. The resulting network, namely vertically stacked optical banyan (VSOB) network, preserves the properties of small depth and absolutely loss uniformity but loses the nice self-routing capability of banyan networks. To guarantee a high switching speed, routing in VSOB network needs special attentions so that paths can be established as fast as possible. The best known global routing algorithm for an N × N nonblocking VSOB network has the time complexity of O(Nlog N), which will introduce an unacceptable long delay in path establishment for a large size optical switch. In this paper, we propose two fast routing algorithms for the VSOB network based on the idea of inputs grouping. The two algorithms, namely plane fixed routing (PFR) algorithm and partially random routing (PRR) algorithm, have the time complexities of O(log N) and O$(\sqrt{N})$ respectively, and FR algorithm can actually turn a VSOB network into a self-routing one. Extensive simulation based on a network simulator indicates that for large VSOB networks our new algorithms can achieve a reasonably low blocking probability while guarantee a very high switching speed.

SUMMARY Internally buffered multistage interconnection network architectures have been widely used in parallel computer systems and large switching fabrics. Migration from electrical domain to optical domain has raised the necessity of developing node architectures with optical buffers. Cascaded fibre delay line architectures can be seen as possible realizations of output and shared buffering in a 2 � 2-switching element. These approaches can be used as buffered node architecture in a Banyan like interconnect. In this paper, we investigate and compare these approaches by using simulation methods. Different performance metrics, such as normalized throughput, average packet delay, packet loss rate and buffer utilization have been used under uniform and non-uniform traffic models. Results show that the TC-chain node Banyan network offer an improved normalized throughput and average packet delay performances under both traffic models without disrupting first-in-first-out order of arrivals. The switched delay-line requires fewer switching elements than TC and TTC architectures but at the cost of high packet delay. Copyright # 2004 John Wiley & Sons, Ltd.

Banyan networks are attractive for constructing directional coupler (DC)-based optical switching networks for their small depth and self-routing capability. Crosstalk between optical signals passing through the same DC is an intrinsic drawback in DC-based optical networks. Vertical stacking of multiple copies of an optical banyan network is a novel scheme for building nonblocking (crosstalk-free) optical switching networks. The resulting network, namely vertically stacked optical banyan (VSOB) network, preserves all the properties of the banyan network, but increases the hardware cost significantly. Though much work has been done for determining the minimum number of stacked copies (planes) required for a nonblocking VSOB network, little is known on analyzing the blocking probabilities of VSOB networks that do not meet the nonblocking condition (i.e., with fewer stacked copies than required by the nonblocking condition). In this paper, we analyze the blocking probabilities of VSOB networks and develop their upper and lower bounds with respect to the number of planes in the networks. These bounds depict accurately the overall blocking behaviors of VSOB networks and agree with the conditions of strictly nonblocking and rearrangeably nonblocking VSOB networks respectively. Extensive simulation on a network simulator with both random routing and packing strategy has shown that the blocking probabilities of both strategies fall nicely within our bounds, and the blocking probability of packing strategy actually matches the lower bound. The proposed bounds are significant because they reveal the inherent relationships between blocking probability and network hardware cost in terms of the number of planes, and provide network developers a quantitative guidance to trade blocking probability for hardware cost. In particular, our bounds provide network designers an effective tool to estimate the minimum and maximum blocking probabilities of VSOB networks in which different routing strategies may be applied. An interesting conclusion drawn from our work that has practical applications is that the hardware cost of a VSOB network can be reduced dramatically if a predictable and almost negligible nonzero blocking probability is allowed.

We show that the problem of finding the maximum passable subset of a permutation through a banyan is NP-complete. We then describe a two-level optical interconnection structure for groups or clusters of end-nodes (LANs or processors). At the higher level, an optical banyan is used to switch wavelength multiplexed packets from the groups. Technologically difficult switching of individual wavelengths is avoided by prearranging transmissions from the groups in a way that they can be switched in a wavelength insensitive manner. Further, by keeping the banyan conflict-free, we allow each of the groups to access the entire set of wavelengths for multiplexing, thus maximizing the bisection bandwidth. The proposed optical interconnect can support multiple multicast connections between each pair of groups, in which source nodes may simultaneously multicast several different packets to different subsets within a destination group. System-wide multicasts and broadcasts can be achieved through repetitive group-to-group transmissions. The network uses readily available components such as opto-electronic directional couplers, fixed wavelength transmitters, and diffraction-based parallel receivers while avoiding the use of relatively slow and expensive tunable components.

The advancement in the field of computer technology, communication and the increasing user demand in terms of bandwidth and speed, the future communication network is rolling towards the BISDN with optical technology. The high speed ATM network is one of the major tool used for BISDN. In turn, the efficiency of the ATM network relies on the switching fabric. Hence, the switching fabric of future telecommunication systems should have a very low cell loss and delay performance. In this paper, the simulation results of Sort Banyan architecture of size 8 × 8 are presented. The simulation of Sort Banyan network is performed along with four different methods in view of enhancing the throughput of the Sort Banyan switch network. The cell loss and delay performance versus the cell arrival rate for the four schemes viz, Input buffer, Interstage buffer, Shared output buffer and Regeneration of cells using FEC method are presented for both Poisson and Self-similar traffic models.

This paper develops an improved analysis of ATM switching architectures adopting a replicated banyan interconnection network provided with dedicated input and output queues, one per switch inlet and outlet. Two different plane selection policies are studied, random choice and alternate sharing, and two different operation modes are considered for the interaction between input and output queues, backpressure and output queue loss. These different internal operations are ranked in terms of traffic performance and the problem of optimal allocation of a given buffer budget between input and output queues is addressed. The analysis, which assumes that the network is loaded by uniform traffic, always provides conservative results whereas known models are less accurate and give optimistic traffic results. Packet delay and loss probability performance is evaluated for the ATM switch and its accuracy is assessed using computer simulation also in comparison with results given by previous models.

Due to the stringent bit-error requirement in fiber optics, preventing the forthcoming crosstalk at switching elements (SEs) is very crucial in the large-scale photonic switches. In this paper, we consider the SE-disjoint multicasting for a photonic Banyan-type switching network. This ensures that at most, one connection holds each SE in a given time thus, neither photonic crosstalk nor link blocking will arise in the switching network implemented with optical devices such as directional couplers, splitters and combiners. Routing a set of connections under such constraint usually takes several routing rounds hence, it is desirable to keep the number of rounds (i.e., scheduling length) to a minimum. Unfortunately, finding the optimal length is NP-complete in general, we propose an algorithm that seeks an approximation solution less than double of the optimal upper bound. The bound permits the Banyan-type multicasting network to be rearrangeable nonblocking as well as crosstalk-free. It is given that the same bound guarantees wide-sense nonblocking for multicast connections, provided that the multicasting capability of the network is restricted to the second half of the whole stages, and strictly nonblocking for one-to-one connections, yet allowing to be free from the crosstalk. We also consider other crosstalk-free multicasting and the link-disjoint multicasting for the Banyan network. The theory developed in this paper gives a unified foundation on designing nonblocking and crosstalk-free photonic Banyan-type networks under the multicast connections.

A smart two-dimensional optical Banyan network is proposed. Polarization switching logic of light is applied for the design of this network. The main element for the connections of the network is an optical crossbar switch that is composed of a half-wave plate, a programmable polarization switch, and a couple of birefringent plates. By the proposed optical crossbar switches, all permutations of the link patterns required in the network are generated due to the optimized design of the switching logic. As a result, complicated routing control of ordinary Banyan networks is much reduced and a simple two-dimensional optical Banyan network with straight interconnections between successive stages of the networks can be realized.

Multistage interconnection networks (Banyan networks) are frequently proposed as connections in multiprocessor systems, in ATM switches, or in Gigabit Ethernet switches. There exist several analytical models for evaluating the performance of such networks. Analytical models are much faster for this purpose than simulation. On the other hand, the development of an analytical model is very time-consuming. In this paper, we present a method for the automatic and fast generation of an analytical network model. The generated analysis handles networks of arbitrary size, arbitrary switching element sizes, arbitrary buffer lengths in each network stage, an arbitrary (but uniform) traffic pattern, and an arbitrarily chosen network load. The arbitrary traffic patterns include multicast traffic, which has not been considered by former models.

Multicast interconnection networks are highly demanded in parallel computing and communication networks. In the paper, we give the necessary and sufficient conditions the rearrangeability of the numbers of planes needed for 2j-cast Banyan-type networks with crosstalk constraints and j being a nonnegative integer. Our results of the paper are extended for multicast connection requests, while the previous study results in the paper of Chen et al. are just for a special case for j = 0 and one-to-one connection requests.

The Blocking Windows Algorithm (BWA) with the fixed-size windows was introduced by Lea in [1] and was used in nonblocking multicast banyan type switching networks. Later, Danilewicz and Kabacin´ski extended BWA to the variable window sizes variant in [2]. Some authors used this concept for different architectures of nonblocking multicast switching networks (Danilewicz, Hwang) [3], [4]. In this paper, performance evaluation of BWA in blocking multicast log 2 (N, 0, p) switching networks is presented. Different settings of BWA have an impact on a performance of the algorithm. In this paper, we investigate which parameters of BWA give better results in terms of blocking probability in blocking multicast log 2 (N, 0, p) switching networks.