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A dual-channel multiplier (DCM) for energy efficient second-order piecewise-polynomial function evaluation for 3-D graphics applications is presented in this paper. The performance of the evaluation process is highly dependent on the design of the multiplication and squaring structure. A novel hardware implementation for polynomial evaluation is presented. The proposed approach compensates the complex multipliers by using DCM which reduces the hardware complexity. The DCM scheme performs complex functions with power-efficient and area-efficient approach. The multiplier reduces the hardware computational effort in the piecewise polynomial approximation with uniform or nonuniform segmentation. For large operand input size, a multiplier adder converter and a dedicated radix-4 squaring unit are also proposed. These units achieve the least power consumption compared to previous approaches with large input word size. Comparison with general purpose multiplication has shown reduction in power, and delay by up to 36%, and 50%, respectively. The proposed technique exhibits up to 93% saving in power consumption compared to the current traditional schemes.

An energy efficient double logarithmic arithmetic (DLA) technique is proposed for 3-D graphics applications. DLA manipulates the logarithmic arithmetic and improves the architecture for the realization of the transcendental functions and the advanced lighting model using energy efficient techniques. The DLA features complete elimination of multipliers in logarithmic domain by using successive logarithmic converters. DLA demonstrates up to 56% reduction in power consumption as compared to the existing techniques. The main advantage of this approach is the ability to perform the complex functions using power-efficient, area-efficient, as well as high frequency design. The proposed technique performs transcendental functions using multiplier free hardware architecture. Moreover, based on nonuniform subdivisions and piecewise linear approximation, novel logarithmic and antilogarithmic converters are also proposed. These converters achieve optimal power consumption as compared to several recent approaches. The proposed converters provide low relative error with less nonuniform subdivisions. Up to 19%, 12%, and 20% reduction in relative error, area, and power consumption are achieved, respectively.

The new field of neuro-prosthetics focuses on the design and implementation of neural prostheses to restore some of the lost neural functions. The electrode-tissue contacts remain one of the major obstacles of neural prostheses microstructure. Recently, Microelectrode fabrication techniques have been developed to have a long-term and stable interface with the brain. In this paper, a comparative analysis of finite element models (FEM) for several electrode layouts is conducted. FEM involves parametric and sensitivity analysis to show the effects of the different design parameters on the electrode mechanical performance. These parameters include electrode dimensions, geometry, and materials. The electrodes mechanical performance is evaluated with various analysis techniques including: linear buckling analysis, stationary analysis with axial and shear loading, and failure analysis for brittle and ductile materials. Finally, a novel figure of merit (FOM) is presented and dedicated to the various electrodes prototypes. The proposed designs take into account mechanical performance, fabrication cost, and cross sectional area of the electrode. The FOM provides important design insights to help the electrodes designers to select the best electrode design parameters that meet their design constraints.

An efficient manipulation of the logarithmic number system (LNS) is proposed resulting in saving in power and area of graphical processing unit (GPU). Double Logarithmic Arithmetic (DLA) approach is presented to achieve low power applications. The proposed scheme exploits the logarithmic field and enhances the computation of the transcendental operations and the lighting pattern operations for energy and area efficiency. The DLA is exploited by means of cascading logarithmic converters to completely eliminate multipliers. Comparison results show that this work achieves up to 51% saving in power and 40% area reduction as compared to the current schemes. The proposed methodology can implement all the transcendental processes utilizing multiplier-free hardware structural.

Logarithmic number system (LNS) is increasingly used for low power arithmetic calculations in graphical processing unit (GPU). LNS requires less hardware. Based on uniform subdivisions and linear-Lagrange interpolation, a novel 8-subdivisions logarithmic/antilogarithmic converters are proposed. Compared with different methodologies, the proposed logarithmic/antilogarithmic converters achieve high accuracy. Also, a significant decrease in area is presented in the comparison between the proposed converters and the prior ones. Hardware implementation using shift-and-add approach is adopted to further simplify the hardware. The novel logarithmic/antilogarithmic converters are implemented and synthesized using 90 nm CMOS technology. Up to 23% and 11% decrease in relative error and area are achieved.

Cubesat is a nano-satellite system standard, where a nano-satellite has structure, power, telemetry, payload among other subsystems, however, it fits up to 1.3 kilograms and 10cm×10cm×10cm modules [1]. Nano-satellites present flexibility in design; in recent years there are several proposals on how to implement the subsystems. The resolution continued to improve, which in turn lead to the need for higher accuracy pointing. They push the bounds of small size and low cost developed to provide cheap access to space and used primarily by universities, these satellites are measured in the tens of centimeters, weigh between one and ten kilograms, and usually cost in the tens of thousands of dollars.