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A fast transient response supply modulator has been realized and verified in envelope elimination and restoration (EER) power amplifier. The analysis and detailed design of the proposed architecture is presented. Simulation results, in 130-nm CMOS technology, show that the proposed supply modulator achieves better linearity and efficiency compared to the conventional hybrid mode supply modulators or hybrid EER when signal frequency increases. Adjacent channel leakage ratio requirements are met for an LTE signal with 5 MHz, 10 MHz, and 20 MHz BW with error vector magnitude less than 3% and efficiency of 79%, 73%, and 67%, respectively at an output power of 0.45 W. Post-layout simulations are performed across different process corners and the effects of real off-chip components and routes are taken into consideration to verify the robustness of the proposed solution.

This paper presents a constant-slope digital-to-time converter (CS-DTC) that leverages the concepts of constant-slope charging and charge redistribution to achieve high linearity with ultra-low power consumption (ULP) that makes the proposed DTC suitable for the Internet-of-Things (IoT) applications. The proposed CS-DTC is designed and simulated in 40-nm technology. It draws 8 μA from a 1.1 V supply when clocked at 50 MHz while achieving 3.7 ps resolution over a 7-bit range. A differential nonlinearity (DNL) and an integral nonlinearity (INL) about 0.2 LSB and 0.3 LSB, respectively, are achieved.

This paper presents the system and circuit level design of a NB-IoT receiver (RX) based on 3GPP Technical Specification (TS) 36.101. This design targets serving many NB-IoT operation bands, so no off-chip filter is used. This dictates large linearity specification on the RF front end to avoid desensitization by −15dBm out-of-band blockers (OOBs). Large linearity specification leads to large power consumption. A solution is proposed to reduce power consumption of the RF front end, while achieving high gain and high linearity. The proposed RF front end provides 29.5dB gain and −10.9dBm IIP3 while consuming 2mW from a single 1.1V power supply. The solution includes adding gain programmability to conventional resistive feedback LNA to relax the trade-off between linearity and power consumption. The RF front end is designed using a 40nm CMOS technology and occupies an area of 0.2mm2.

This paper presents a new integrated RF energy harvesting system using a rectifier with reconfigurable stages. The design replaces the diode-connected transistors used in conventional RF-DC rectifiers with diode-emulated transistors for minimizing conduction losses. In addition, a voltage feedback loop is employed to regulate the output voltage at the main load. Extra available power is provided to a secondary storage unit (supercapacitor). The system is implemented in a 130nm CMOS technology, and circuit simulations show that the proposed design achieves a peak power conversion efficiency (PCE) of 29% at 0dbm input power, and a load regulation of 10mV.

This paper presents a compact N-way Wilkinson power divider using symmetric lumped sections for mm-wave applications. As a proof of concept, an 8-way Wilkinson power divider is implemented covering the n260 5G band. The design area is 0.15×0.15 mm2 in 45nm-SOI CMOS technology. For 25% fractional bandwidth, the proposed Wilkinson divider achieves an insertion loss less than 2.1 dB, input/output return loss better than 10 dB, and isolation better than 25 dB between the different output ports.

This paper presents a fully integrated power management system suited for biomedical implanted devices. The proposed system employs a reconfigurable capacitor-based step-up DC-DC converter. The proposed DC-DC converter can provide fractional voltage conversion ratio (VCR) in a step of 0.25 to support wide input range from 0.4-1.2 V providing a constant output voltage of 1.6 V. The system efficiency is optimized using a real-time monitoring for the input current supplied to the DC-DC converter. This allows the system, using a control sequence, to adaptively optimize the number of stages and switching frequency that will provide the required constant output voltage while maintaining optimum efficiency. The proposed system is designed using a 180nm CMOS technology. Simulation results show that the proposed system provides peak efficiency of 78.1%.

In this paper an automated CAD tool that can be used in integrated circuit technology characterization is proposed. The proposed methodology fills the gap found in old, as well as, new IC design methodologies. The tool allows the user to perform a rapid and full characterization for different device models available in a process design kit (PDK). A set of pre-defined suite of test-benches are created to cover different aspects of circuit design. A seamless integration of the tool in typical design environments is achieved using SKILL code and OCEAN script. Moreover, the tool can compare different PDK releases or different technologies in terms of DC/AC performance, high frequency operation, leakage, and layout area efficiency. The paper presents the tool structure, interface, and capabilities. Finally, a characterization example is applied to CMOS 130 nm technology; results are shown for different devices characterization: MOSFET, BJT, Diode, Resistor, and Capacitor.

This brief introduces a design approach for Class-AB-style ring amplifiers which differs from the design of conventional amplifiers. The theory of operation of Class-AB-style ring amplifier is discussed as well as the different design tradeoffs that affect its design. Consequently, a systematic design methodology for Class-AB-style ring amplifier is introduced. A design example of a switched-capacitor gain amplifier with a closed-loop gain of 32, using a three-stage self-biased ring amplifier, is presented. This example has been designed and implemented in UMC 130-nm CMOS technology. It achieves an spurious-free dynamic range of 72 dB with a clock frequency of 25 MHz. It operates from a single 1.2-V supply and consumes 400 $\boldsymbol \mu \text{A}$ .

A bottom-up system verification approach for ultrawideband massive MIMO millimeter-Wave transceivers is presented. The proposed methodology allows flexible co-simulation among multi-domains taking into consideration real-time nonidealities, and their corresponding effects on the signal integrity. The modelling of a hybrid $8\times 8$ beam former including OFDM signal generation, power amplifier, phased array antennas, is shown as an example demystifying design complexities and challenges.

In this paper, a fast optimization technique for CMOS analog circuits sizing is presented. The technique is based on geometric programming (GP) optimization. Although GP sizing is a very fast method, it produces inaccurate optimal solution due to the lack of accurate MOSFET equations. The proposed technique generates accurate geometric programming (GP) compatible MOSFET equations. Generation of device equations has two phases; look-up table (LUT) generation phase and monomial data fitting phase. The first phase is completed once per technology model. The second phase is performed during the circuit optimization process. A two-stage op-amp is optimized to test the performance of the proposed technique. The simulation results show that the circuit performance achieved using the proposed technique is better than the circuit performance reported in literature, and that the optimal solution is found in less computation time.

In this paper, two different classifiers are software and hardware implemented for neural seizure detection. The two techniques are support vector machine(SVM) and artificial neural networks(ANN). The two techniques are pretrained on software and only the classifiers are hardware implemented and tested. A comparison of the two techniques is performed on the levels of performance, energy consumption and area. The SVM is pretrained using gradient ascent (GA) algorithm, while the neural network is implemented with single hidden layer. It is found that the ANN consumes more power than the SVM by a factor of 4 with almost the same performance. However, the ANN finishes classification in much less number of clock cycles than the SVM by a factor of 34.

This paper presents a novel design of an ultra-broad-band class-D power amplifier (PA). The proposed architecture is based on the concept of the ripple buck converter after employing some modifications to facilitate supporting bandwidths up to tens of MHz. The input frequency range covered using the proposed class-D PA is from 0.5MHz up to 30MHz. A wide-band transformer has been used to convert the differential outputs of the class-D PA to single-ended load. The design has been implemented and fabricated using a CMOS 0.13µm technology. It occupies an active area of 0.836mm2 and operates from a single 1.2V supply. The measurement results validates the functionality of the proposed class-D PA with good linearity and peak efficiency of 58% at 140mW of output power. This has been achieved using few off-chip passive components.

A multi-band CMOS power amplifier has been realized to be used in high-efficiency handset applications. The proposed PA is based on class-E stage linearized using envelope elimination and restoration (EER) technique. In order to cover multiple frequency bands, a wide-band passive output matching network is designed and combined with band-select feature. This allows switching between two wide-band output matching networks; increasing frequency coverage and yet satisfying the criteria of high rejection of out-of-band emissions. A design methodology is introduced to optimize the values required for the wide-band passive network. The design has been implemented using CMOS 0.13 μm technology. Simulation results show frequency coverage from 800 MHz to 2.2 GHz with peak efficiency more than 60% (before taking the effect of supply modulator) and 47% after taking the losses of the supply modulator into account. The designed EER system achieves excellent linearity performance. The test and validation process includes LTE test signal with 16 QAM modulation scheme and signal bandwidth of 20 MHz.

Authenticated Encryption (AE) and Authenticated Encryption with Associated Data (AEAD) play a significant role in cryptography as they simultaneously provide confidentiality, integrity, and authenticity assurances on the data. The Competition for Authenticated Encryption, Security, Applicability, and Robustness (CAESAR) seeks optimal authenticated ciphers based on multiple criteria, including security, performance, area, and energy-efficiency. In this paper, low area and low power implementations of selected ciphers from the CAESAR candidates namely NORX, Tiaoxin, SILC, and COLM are provided. A reduction in area with an average of 43% and a reduction in dynamic power with an average of 54% are achieved compared to their corresponding high-speed architectures. Moreover, throughput (TP) in (Mbps) decreases by an average of 68% and throughput-to-area (TP/A) in (Mbps/Slices) decreases by an average of 48 %.

Dynamic Partial Reconfiguration (DPR) on Field Programmable Gate Arrays (FPGAs) allows some of the logic to be configured while the rest of the logic keeps operating. This kind of designs are called Dynamically Reconfigurable System (DRS) designs, they can operate in multiple modes. The verification of the DRS designs is a complicated task due to the need to verify all the modes of the designs, and the lack of Computer Aided Design (CAD) tools support for DRS designs. In this paper, we propose an automatic Clock Domain Crossing (CDC) verification flow for DRS designs. A Perl utility is implemented which automates the generation of the designs files for each operating mode of the design, generates the script to run CDC analysis on the design, runs a CDC analysis tool, and collates the results in a user-friendly representation for debugging.

In this paper, both linear and nonlinear features have been reviewed with linear support vector machine (SVM) classifier for neural seizure detection. The work introduced in the paper includes performance measurement through different metrics: accuracy, sensitivity, and specificity of multiple linear and nonlinear features with linear support vector machine (SVM). A comparison is performed between the performance of different combinations between 11 linear features and 9 nonlinear features to conclude the best set of features. It is found that some features enhance the detection performance greatly. Using a combination of 3 features of them, a linear SVM classifier detects seizures with sensitivity of 96.78%, specificity of 97.9%, and accuracy of 97.9%.

Dynamic Partial Reconfiguration (DPR) on Field Programmable Gate Arrays (FPGAs) allows reconfiguration of some of the logic at runtime while the rest of the logic keeps operating. This feature allows the designers to build complex systems such as Software Defined Radio (SDR) in a reasonable area. However, utilizing DPR needs more verification efforts to ensure the correct operation of the reconfiguration logic and the design functionality. New scenarios should be covered due to the usage of DPR technique such as guaranteeing proper connections for the ports of the Reconfigurable Modules (RMs) which share the same Reconfigurable Region (RR) on the FPGA. This paper proposes a technique to verify the connections of the RMs using Assertion Based Verification (ABV). The proposal is to first model the connections of the RMs using System Verilog Assertions (SVAs), then instrument the design with the generated assertions, and then verify the instrumented design using formal verification methods to prove or disprove the correctness of the connections. The proposed technique is demonstrated on a real design that utilizes DPR technique.

Debugging of Field-Programmable Gate Arrays (FPGAs) is a difficult task due to the limited access to the internal signals of the design. Embedded logic analyzers enhance the signal observability for FPGAs. These analyzers are implemented on the FPGA resources and they use the embedded memory blocks as trace buffers, so a limited number of signals can be observed using these analyzers due to resources constraints. Changing the traced set of signals requires re-synthesis, placement and routing of the whole design. In this paper, we propose a new methodology for FPGA debugging to change dynamically the set of signals to be observed at runtime, and consequently minimize the time required for debugging. The proposed methodology utilizes the Dynamic Partial Reconfiguration (DPR) technique to dynamically switch between different sets of signals. DPR creates a reconfigurable module (RM) to route each set of signals to an embedded logic analyzer. We demonstrate the proposed approach using Xilinx FPGA tools, finding that changing the set of signals to be observed requires only few milli-seconds to re-program the reconfigurable region (RR). The area overhead of the proposed methodology is lower than other traditional methods of using multiplexers as the DPR allows the routing module to only use buffers to connect a set of signals to the embedded logic analyzer.

This paper presents an ultra-low-power receiver operating at the 2.4 GHz ISM band for internet of things (IoT) and wireless sensor nodes (WSN) applications. It complies with ZigBee 802.15.4 standard, while consuming 2.7mW from a single 1.2 voltage supply. A low-IF system architecture was chosen as a compromise between low power consumption and good performance. The receiver consists of a low-noise-amplifier (LNA), double balanced IQ mixer, complex filter, variable gain amplifier, and an analog-to-digital converter (ADC). It has been implemented in 65nm CMOS technology and occupies an active area of 0.89 mm2.

Dynamic Partial Reconfiguration (DPR) on Field Programmable Gate Arrays (FPGAs) allows reconfiguration of some of the logic at runtime while the rest of the logic keeps operating. This feature allows the designers to build complex systems such as Software Defined Radio (SDR) in a reasonable area. However, utilizing DPR needs extra care to be taken for new issues such as waiting for running computations on a module before reconfiguring it, isolation of the reconfigurable modules during the reconfiguration process, and initialization of the reconfigurable module after the reconfiguration process is done. This paper proposes a technique to verify these newly introduced issues using Assertion Based Verification (ABV). The proposed technique proves effectiveness in finding issues on real designs that utilize DPR technique.

This paper presents a novel ring amplifier for continuous-time (CT) circuits. The proposed amplifier enables the usage of ring amplifier in continuous-time applications. The design parameters of the proposed architecture are discussed and analyzed. A CT second order Sigma-Delta (ΣΔ) modulator is designed using the proposed architecture achieving SNDR of 61.7 dB at signal BW of 1 MHz and sampling frequency of 104 MHz. The modulator is implemented in a 65 nm CMOS process and consumes 490 μW from a single 0.9 V power supply.

In this paper an automated CAD tool for rapid technology characterization is presented. The proposed methodology fills the gap found in old, as well as, new IC desgin methdologies technology. The tool allows the user doing a rapid characterization for different devices models available in a technology. The tool is based on a pre-defined suite of test-benches in addition to SKILL code and OCEAN script to allow seamless integration of the tool in the design environment. Finally, a design example is presented using 130 nm CMOS technology using the tool; results are shown for MOSFET devices characterization.

In this paper, an active filtering technique is presented which is capable of filtering the out-of-band blockers in wireless receivers. The concept is based on the feedforward cancellation technique where a blocker replica is subtracted at the output of the low-noise amplifier (LNA). In contrast to the previously reported feedforward cancellation methods, exact gain and phase matching are easily obtained in the proposed architecture to produce a highly selective narrowband frequency response at the output of the LNA with wide rejection bandwidth. For the proof of concept, the system is implemented in a 65nm CMOS technology. It occupies a total area of 0.8mm^2 and the current consumption is 24mA from a 1.2V supply. The system post-layout simulations showed a blocker rejection of more than 33dB for blocker signals 100MHz away from the desired signal when the feedforward path is activated. The noise figure (NF) of the entire system is 3.8dB that degrades to 5.8dB when the feedforward path is activated.

A pulse-resonance On-Off keying ultrasound communication microsystem is presented. It is a viable alternative to today’s widely used RF technologies in order to avoid the associated health risks for a specific group of interest, namely babies. Special signal processing and circuit techniques are proposed to overcome drawbacks of classical ultrasound communications; such as echoes and excess ringing, achieving a measured communication range of 28m with a 50bits/s data rate and bit error rate (BER) of 0.01. Targeting a biomedical sensory pacifier, the proposed design needs to be insulated, small size, and low power. Utilizing a 40 kHz ultrasound transducer and a 5-pin low-power controller, a wirelessly-charged high-accuracy remote temperature sensor system with nominal average current consumption of 0.416μA is designed and tested. Multiple subsystems were merged in total volume of 12mm diameter and 15mm height, excluding the charging coil, which is designed as the pacifier’s handler. Thanks to echo avoidance, ringing suppression, dynamic detection threshold adjustment techniques along with 3-bit preamble synchronization; the proposed low-power sub-sampling IQ demodulation of OOK bits results in high-sensitivity robust ultrasound communication system without any alignment requirement for the transducers. The lifetime of the sensor prototype with 8mAh LiR battery is about 27 months.

This brief proposes a scalable multichannel clock and data recovery architecture that exploits the synchrony of multiple point-to-point serial links and uses a single voltage-controlled oscillator (VCO) to drive multiple phase detection loops. The proposed architecture can be naturally reduced by design to an ensemble of weakly interacting delay-locked loops. As a result, the jitter peaking problem is asymptotically eliminated, which makes this architecture well suited for use in long-haul repeater chains. Moreover, it allows controlling VCO jitter transfer to the recovered clock without affecting data jitter transfer. The architecture is demonstrated both by a Verilog-A behavioral model along with a rigorous system and statistical analysis.

A low-power quadrature direct digital frequency synthesizer (DDFS) is presented. Piecewise linear approximation is used to avoid using a ROM look-up table to store the sine values as in a conventional DDFS. Significant saving in power consumption, due to the elimination of the ROM, renders the design more suitable for portable wireless communication applications. To demonstrate the proposed technique, a quadrature DDFS has been implemented using 0.5-/spl mu/m CMOS process and occupies an active area of 1.4 mm/sup 2/. It consumes 8 mW at 100 MHz and operates from a single 2.7-V supply. The spurious-free dynamic range is better than 59 dBc at low synthesized frequencies and the frequency resolution is 1.5 kHz.