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In recent years, IEEE 802.15.4-based Wireless Sensor Networks (WSN) have experienced significant growth, mainly motivated by the standard features, such as small size oriented devices, low power consumption nodes, wireless communication links, and sensing and data processing capabilities. In this paper, the development, implementation and deployment of a novel fully compatible IEEE 802.15.4-based WSN architecture for applications operating over extended geographic regions with high node mobility support, is described. In addition, a practical system implementation of the proposed WSN architecture is presented and described for experimental validation and characterization purposes.

A novel variable length packet scheduling algorithm focused on real output queue reference architecture is presented in this paper. The main features of this packet scheduler development are the Quality of Service (QoS) and variable length packet support. The packet scheduler supports up to eight traffic classes which can be assigned up to two different priorities. The bandwidth assigned to any traffic class is configurable. The packet scheduler has been described and simulated in C++ language under uniform and bursty traffic conditions.

Classification of Internet protocol (IP) packets has become a bottleneck for the effective operation of QoS capable routers. In this paper, a novel packet classification scheme for high performance routers on different QoS architectures, named split-engine packet classification (SPC), is proposed. The key feature of the presented architecture is its ability to address a wide variety of inherently incompatible performance requirements by efficiently combining existing classification methods. To prove the validity of the proposed approach, a low cost SPC packet classifier architecture with per-flow packet treatment and dynamic resource reservation support on an OC-24 link as required by the Integrated Services framework, has been developed.

Scheduling algorithms developed for virtual-output-queuing (VOQ) switches have focused on the throughput enhancement, rather than provide QoS guarantees for different priority levels. Presented, is a new scheduling scheme to effectively support real-time and data applications in VOQ switches with negligible complexity increment.

Virtual output queue (VOQ) is an efficient architecture for high-speed switches because it combines the low cost of input-queuing with high performance of output-queuing. The achievable throughput and delay performance heavily depends on the scheduling algorithm used to resolve the contention for the same output ports in each cell slot. Most VOQ scheduling algorithms, as exemplified by PIM and iSLIP, re based on parallel and iterative request-grant-accept arbitration schemes. Conventional performance evaluation of these scheduling algorithms, does not consider the effect of some issues inherent to their implementation on a modular and scalable VOQ switch with input ports and switch matrix residing on separate cards. One of the main issues is the Round-Trip Delay (RTD), defined as the latency between a connection is requested to the switch matrix card and the associated acceptance notification is received on the input port card. In this paper, the effect of RTD on performance parameters for PIM and iSLIP algorithms is presented, not being considered in deep in previous works appearing In the literature. Based on simulation results, RTD is demonstrated to affect significantly contention on output ports and mean queuing delay, and thus degrade the performance of cell-based VOQ switches.