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The simulation system is one of the important means to develop the weapon system. The distributed real-time simulation system can greatly accelerate the weapon research process. Distributed real-time simulation systems based on UDP and fiber-optic reflective memory networks enhance system computing, resource scheduling, and network communications. Based on the reflective memory network and Ethernet, the simulation system uses dual network transmission. Finally, the experimental results show that the system is real-time, communication is stable, high-speed, reliable, and the simulation system meets the requirements of multi-missile simulation.

In order to improve the real-time performance and reliability of the drive system for infrared image array, this paper designs an embedded drive system. With MPC8315 as the processing core, this system takes reflective memory network as the transmission unit. In order to verify and analyze the performance of the embedded drive system for the infrared image array, this paper sets up a test platform. Compared to the existing system, the real-time performance and drive capability of the embedded drive system designed in this paper are largely improved.

According to the requirement of real-time performance and universality in the virtual simulation system, the communication card adopts reflective memory technology with the ability to build the reflective memory network. At the same time, according to the requirement of interaction between virtual model and physical model, the card has serial interface and the ability of interaction with reflective memory network through serial interface. The experiments proved that the multifunctional communication card’s bandwidth is up to 30 MB/s, its bit error rate is lower than 10−15, its time delay is up to the rank of the deep microsecond.

On the hardware platform of Distributed Real-Time Simulation, a communication module based on reflective memory network was realized in FPGA. As an infrastructure module, it could be integrated with other modules seamlessly. Under the speed-first rules, DMA engine in PCI Master mode was designed, and 64bits/32bits bus compatibility was realized. In order to solve the competition problems during network and memory access, the Arbiter strategy based on adjustable time slice was proposed. In addition, network command packets of higher priority were introduced to fit practical simulation requirements, including the interrupts issue.

The demonstrator of a reflective memory board for particle accelerators data acquisition and control system applications is presented. The main building blocks of the reflective memory board are: a 32 bit times 66 MHz Master/Target PCI interface with DMA capabilities, a fiber optic full-duplex high-speed link and a 1 MByte synchronous static DPRAM. The reflective memory mechanism is implemented in a fully transparent way in both directions. A message passing and remote interrupt generation procedure from one PC to the other is implemented too