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MPSoCs with hierarchical communication infrastructures are promising architectures for low power embedded systems. Multiple CPU clusters are coupled using an Network-on-Chip (NoC). Our CoreVA-MPSoC targets streaming applications in embedded systems, like signal and video processing. In this work we introduce a tightly coupled shared data memory to each CPU cluster, which can be accessed by all CPUs of a cluster and the NoC with low latency. The main focus is the comparison of different memory architectures and their connection to the NoC. We analyze memory architectures with local data memory only, shared data memory only, and a hybrid architecture integrating both. Implementation results are presented for a 28 nm FD-SOI standard cell technology. A CPU cluster with shared memory shows similar area requirements compared to the local memory architecture. We use post place and route simulations for precise analysis of energy consumption on both cluster and NoC level using the different memory architectures. An architecture with shared data memory shows best performance results in combination with a high resource efficiency. On average, the use of shared memory shows a 17.2 percent higher throughput for a benchmark suite of 10 applications compared to the use of local memory only.

In this article we compare a scalable FPGA-based hardware accelerator for the emulation of Self-Organizing Feature Maps (SOMs) with a multi-threaded software implementation on a state-of-the-art multi-core microprocessor. After discussing the mapping of SOMs to the reconfigurable digital hardware implementation, we present how the modular system architecture can be flexibly adapted to various application datasets as well as to variants of SOMs like Conscience SOM. Hyperspectral image processing is used as a benchmark scenario for the comparison of our FPGA-based hardware accelerator and state-of-the-art multi-core microprocessors. The hardware costs, power consumption, and scalability of the FPGA based accelerator using Xilinx Virtex-4 FPGAs are discussed. For the real-world datasets used here, which require large SOMs, a speedup and energy reduction of one order of magnitude is achieved.

Conference of 16th International Conference on Embedded Computer Systems: Architectures, Modeling and Simulation, SAMOS 2016 ; Conference Date: 17 July 2016 Through 21 July 2016; Conference Code:126004; International audience; The Modular Microserver DataCentre (M2DC) project investigates, develops and demonstrates a modular, highly-efficient, cost-optimized server architecture composed of heterogeneous micro server computing resources, being able to be tailored to meet requirements from various application domains, including the Internet of Things. M2DC is built on three main pillars: a flexible server architecture that can be easily customised, maintained and updated; advanced management strategies and system efficiency enhancements (SEE); well-defined interfaces to surrounding software data centre ecosystem.

In this article, we present the prototypical implementation of the scalable GigaNetIC chip multiprocessor architecture. We use an FPGA-based rapid prototyping system to verify the functionality of our architecture in a network application scenario before fabricating the ASIC in a modern CMOS standard cell technology. The rapid prototyping environment gives us the opportunity to test our multiprocessor architecture with Ethernet-based data streams in a real network scenario. Our system concept is based on a massively parallel processor structure. Due to its regularity, our architecture can be easily scaled to accommodate a wide range of packet processing applications with various performance and throughput requirements at high reliability. Furthermore, the composition based on predefined building blocks guarantees fast design cycles and simplifies system verification. We present standard cell synthesis results as well as a performance analysis for a firewall application with various couplings of hardware accelerators. Finally, we compare implementations of our architecture with state-of-the-art desktop CPUs. We use simple, general-purpose applications as well as the introduced packet processing tasks to determine the performance capabilities and the resource efficiency of the GigaNetIC architecture. We show that, if supported by the application, parallelism offers more opportunities than increasing clock frequencies.

Tightly coupling CPUs within clusters allows for low latency, high bandwidth communication in MPSoCs. Our CoreVA-MPSoC integrates multiple clusters using an on-chip network. In this work we introduce a shared L1 data memory that can be accessed by all CPUs of a cluster with low latency. A Mesh-of-Trees (MoT) and a crossbar as topology for the shared memory interconnect are presented. A cluster that integrates the shared L1 memory is compared with an architecture that features an AXI interconnect and a local L1 data memory for each CPU. In addition, we consider an architecture that integrates both. We present implementation results using a 28nm FD-SOI standard cell technology. The shared L1 memory shows similar area results compared to the local memory architecture. Place and route results of a cluster with 8 CPUs, 128kB local-and 128kB shared L1 data memory divided into 16 memory banks show a frequency of 728MHz and an area of 1.77mm2. To map programs to the different CPU cluster configurations a compiler for streaming applications is used. An architecture with both local and shared L1 data memory and 4 memory banks shows best performance results in combination with a high resource efficiency.

Reconfigurable architectures are increasingly employed in a large range of embedded applications, mainly due to their ability to provide high performance and high flexibility, combined with the possibility to be tuned according to the specific task they address. Reconfigurable systems are today used in several application areas, and are also suitable for systems employed in safety-critical environments. The actual development trend in this area is focused on the usage of the reconfigurable features to improve the fault tolerance and the self-test and the self-repair capabilities of the considered systems. The state-of-the-art of the reconfigurable systems is today represented by Very Long Instruction Word (VLIW) processors and reconfigurable systems based on partially reconfigurable SRAM-based FPGAs. In this paper, we present an overview and accurate analysis of these two type of reconfigurable systems. The content of the paper is focused on analyzing design features, fail-safe and reconfigurable features oriented to self-adaptive mitigation and redundancy approaches applied during the design phase. Experimental results reporting a clear status of the test data and fault tolerance robustness are detailed and commented.

Modern high-performance embedded systems are characterized by heterogeneity of the employed processing elements: general-purpose processors working together with embedded processors and with dedicated hardware accelerators or high-speed I/O interfaces. Communication among these processors and interfaces is one of the crucial aspects of the development of such systems. In this paper we present a communication interface for heterogeneous embedded multiprocessor systems. The interface is intended to be used to synchronize the data-flow between hardware accelerators and high-speed I/O interfaces. The interface has been designed with the aim of finding a trade-off between performance, flexibility and usability. In order to assess its performance and usability, the interface has been implemented and applied to a heterogeneous multiprocessor architecture used for payload processing in satellite systems.

Many applications of self-organizing maps (SOM) require high computing performance in order to be efficient. Because of the regular and modular structure of SOMs, a custom hardware realization is obvious. Based on the idea of a massively parallel system, several chips have been designed, manufactured and tested by the authors. In this article a high-performance system with the latest NBISOM_25 chips is presented. The NBISOM_25 integrated circuit (ES2 1.0 μm CMOS) contains 25 processing elements in a 5×5 array. Due to the scalability of the chips a VMEbus board was built with 16 ICs on it. The controllers for the VMEbus and the SOM hardware are realized using FPGAs. The system runs SOM applications with up to 400 elements in parallel mode (20×20 map). Each model vector can have up to 64 weights of 8 bit accuracy. The maximum performance of the board-system is 4.1 GCPS (recall) and 2.4 GCUPS (learning). It is integrated in a simulation framework for neural networks, that contains software tools for self-organizing maps as well as for neural associative memories, tools for pre- and postprocessing and tools for graphical analysis of the simulation results.

In this work we present a design space exploration of the memory subsystem of our configurable CoreVA VLIW architecture. The development of resource efficient processor architectures is based on a two-stage tool flow using a high-level processor specification as a reference. We evaluate several memory configurations like one memory port or two memory ports, as well as different write-miss-allocation modes. Applications ranging from LTE protocol stack over baseband processing up to cryptography and multimedia are evaluated in terms of execution time and energy efficiency. Analyses have shown that the application specific configuration of the memory subsystem can improve energy by up to 25%. Our environment allows the rapid profiling and evaluation of algorithms to choose the most efficient configuration.

Nowadays, the Network-on-Chip (NoC) paradigm has become more and more popular for building an on-chip communication infrastructure. Like in every traditional network, debugging and performance monitoring are also very important issues in NoC-based systems. Unfortunately, the design process of monitoring hardware is a time consuming activity. The work presented in this paper is based on a high level specification language, called SiLLis (Simplified Language for Listeners), for the convenient development of generic monitoring hardware. SiLLis allows the designer to define complex filter rules on a high abstraction level. In this way, the design time as well as the bandwidth requirements for monitoring data can be drastically reduced. To present the benefits of SiLLis, we define a performance monitor that is integrated into a NoC-based multiprocessor System-on-Chip and can be used both to analyze the performance of the system and to optimize the routing strategy at run-time. By using SiLLis, the performance monitor can be realized with a area overhead of only 0.58 % per NoC node.

To meet application-specific performance demands, architectures are predominantly redesigned and customised. Every architectural change results in huge overheads in design, verification, and fabrication, which together result in prolonged time-to-market. As an alternative, configurable architectures provide easy adaptability to different application domains in place of costly redesigns. To deal with application changes and custom requirements, a method of configuring and reusing the basic building blocks within processors is developed. Additionally, this enables co-operative multiprocessing. In this paper, a runtime reconfiguration mechanism for embedded multiprocessor architectures is proposed as a method to introduce customisations in the post-fabrication phase. A method of application description in conjunction with a flexible reconfigurable multiprocessor template is presented. Finally, the costs and benefits of this approach are analysed for computationally intensive algorithms used in digital signal processing. The impact of application specific characteristics on execution time, power consumption, and total energy dissipation are analysed.

A hardware accelerator for self-organizing feature maps is presented. We have developed a massively parallel architecture that, on the one hand, allows a resource-efficient implementation of small or medium-sized maps for embedded applications, requiring only small areas of silicon. On the other hand, large maps can be simulated with systems that consist of several integrated circuits that work in parallel. Apart from the learning and recall of self-organizing feature maps, the hardware accelerates data pre- and postprocessing. For the verification of our architectural concepts in a real-world environment, we have implemented an ASIC that is integrated into our heterogeneous multiprocessor system for neural applications. The performance of our system is analyzed for various simulation parameters. Additionally, the performance that can be achieved with future microelectronic technologies is estimated.

Information processing and networking of technical devices find their way into our daily life. In order to process the continuously growing quantity of data, powerful communication nodes for network processing are needed. We present an architecture for network processors that is based on a uniform, massively parallel structure. Thus, our approach takes advantage of reusing predefined IP building blocks. This leads to a short time to market, a high reliability and a scalable architecture. Our architecture is scalable to different areas of application by varying the number of integrated processors. Additionally, specific hardware accelerators can be embedded, which are optimized for the target application, in order to be especially resource-efficient in respect to power consumption, computational power and required area.

The GigaNetIC project aims to develop high-speed components for networking applications based on massively parallel architectures. A central part of this project is the design, evaluation, and realization of a parameterizable network processing unit. In this paper we present a design methodology for network processors which encompasses the research areas from the application software down to the gate level of the chip. Key components of this holistic approach have been successfully applied to characteristic examples of architecture refinements.

The hardware implementations of three different artificial neural networks are presented. The basis for the implementations is the reconfigurable hardware accelerator RAPTOR2000, which is based on FPGAs. The investigated neural network architectures are neural associative memories, self-organizing feature maps and basis function networks. Some of the key implementation issues are considered. In particular, the resource efficiency and performance of the presented realizations are discussed.

Today's deep submicron fabrication technologies enable design enginefrs to put an impressive number of eomponfnts like micropmeessors, memories, and interfaces on a single microchip. With the emergence of 100 nm processes, billions oftransistors can be integrated on one die and form a parallel system, consisting out of thousands of components. To handle this impressive number of components it is important to provide a communication infrastructure which is able to scale with the capabilities of upcoming fabrication technologies and which provides the foundation for efficient on-chip communication protocols. This paper addresses the architectural requirements which are coupled with the transfer of well known techniques from parallel computers unto the design of Secs and proposes an on-chip architecture which is based on active switch bores. We will show that this architecture is able lo fill the existing design gap between an efficient use of the design space and the design complexity with reasonable resource requirements.

This paper describes a framework for the design space exploration of resource-efficient software-defined radio architectures. This design space exploration is based on a dual design flow, using a central processor specification as reference for the hardware development and the automatic generation of a C-compiler based tool chain. Using our modular rapid prototyping environment RAPTOR and the RF-frontend DB-SDR, functional verification of SDR applications can be performed. An 802.11b transmitter SDR implementation is mapped on our CoreVA a VLIW architecture and evaluated in terms of execution time and energy consumption. By introducing application specific instruction set extensions and a dedicated hardware accelerator, execution time and energy consumption could be reduced by about 90%.