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In recent years, convolutional neural networks (CNNs) have achieved significant advancements in various fields. However, the computation and storage overheads of CNNs are overwhelming for Internet-of-Things devices. Both network pruning algorithms and hardware accelerators have been introduced to empower CNN inference at the edge. Network pruning algorithms reduce the size and computational cost of CNNs by regularizing unimportant weights to zeros. However, existing works lack intrakernel structured types to tradeoff between sparsity and hardware efficiency, and the index storage for irregularly pruned networks is significant. Hardware accelerators leverage the sparsity of pruned CNNs to improve energy efficiency. However, their process element (PE) utilization rate is low because of uneven sparsity among input convolutional kernels. To overcome these problems, we propose PACA: a Pattern pruning Algorithm and Channel-fused high PE utilization Accelerator for CNNs. It includes three parts: a pattern pruning algorithm to explore the intrakernel sparsity type and reduce the index storage, a channel-fused hardware architecture to reduce the PEs’ idle rate and improve the performance, and a heuristic and taboo search-based smart fusion scheduler to analyze the idle PE problem and schedule the channel fusion in hardware. To demonstrate the effectiveness of PACA, we have implemented the software parts by Python and the hardware architecture by RTL codes. Experimental results on various datasets show that compared with an existing work, PACA can reduce the index storage overhead by $3.47\times $ – $5.63\times $ with 3.85–9.12 average patterns, and it can improve the hardware performance by $2.01\times $ – $5.53\times $ because of PEs’ idle rate reduction. [ABSTRACT FROM AUTHOR]

Computing-in-memory (CIM) is a promising architecture for energy-efficient neural network (NN) processors. Several CIM macros have demonstrated high energy efficiency, while CIM-based system-on-a-chip is not well explored. This work presents a CIM NN processor, named STICKER-IM, which is implemented with sophisticated system integration. Three key innovations are proposed. First, a CIM-friendly block-wise sparsity (BWS) architecture is designed, enabling both activation-sparsity-aware acceleration and weight-sparsity-aware power-saving. Second, an adaptive kernel-/channel-order (KCO) mapping and intra-/inter-macro scheduling strategy is proposed to improve macro utilization and data reuse. Third, an efficient BWS-optimized CIM (BWS-CIM) macro with adaptive power-OFF ADCs is implemented. The STICKER-IM chip was fabricated in 65-nm CMOS technology. Experimental results show 5.8–158-TOPS/W average system energy efficiency on the sparse NN models. The macro/system-level energy efficiency is $4.23\times / 3.06\times $ higher compared with the state-of-the-art CIM macros and processors. [ABSTRACT FROM AUTHOR]

The emerging edge intelligence requires low-cost energy-efficient neural network (NN) processors. Supporting various types of edge NN models leads to extra circuit overhead. Designing a unified NN processor with high energy/area efficiency is challenging. This work presents a frequency-domain-accelerated unified NN processor, named STICKER-T. It combines algorithm, architecture, and circuit-level optimization to achieve high energy/area efficiency. By utilizing the block-circulant NN (CirCNN) algorithm, this work supports frequency-domain acceleration and a unified workflow for convolutional, fully connected, and recurrent NN (CNN/FC/RNN). Three key innovations are proposed. First, a block-circulant-accelerated chip architecture is implemented to support unified CNN/FC/RNN workflow. Second, a multi-bit 8-128-point global-parallel local-bit-serial fast Fourier transform (FFT) module is designed for efficient high-throughput FFT/inverse FFT (IFFT) operation. Third, by utilizing a 6T hierarchical-bitline-switching transpose-SRAM (HBST-TRAM), 2-D data reuse is enabled in the proposed multi-bit frequency-domain multiply–accumulate (MAC) array. STICKER-T was fabricated in a 65-nm CMOS technology. It can operate at 0.54–1.15 V and 25–200 MHz with 13.3–339-mW power consumption. The peak energy efficiency achieves 140.3 TOPS/W. It shows 8.1 × area efficiency and 4.2 × energy efficiency at 4-bit precision compared with the state-of-the-art reconfigurable NN processor. [ABSTRACT FROM AUTHOR]

Owing to its unique capability to sustain computation progress over power outages, a nonvolatile processor (NVP) is promising for energy-harvesting-powered Internet-of-Things devices. However, the widespread application of NVP is continually blocked by the system integration issues and the configuration overheads of peripheral devices. This paper presents a nonvolatile system-on-chip (NVSoC) with improved integration level, power management flexibility, and system wake-up speed. An on-chip power management subsystem is designed to minimize the number of external components while supporting versatile power policies. And a direct peripheral restore architecture is outlined, which enables a fast and parallel re-configuration of peripheral devices after the resumption of power supply. A test chip is fabricated in a 130-nm ferroelectric-CMOS process with 22.09-mm2 area. Measurement results show 6 $\times $ higher data throughput as compared with a conventional NVP when facing power failures. [ABSTRACT FROM AUTHOR]

In this letter, the write disturb of Hf0.5Zr0.5O2-based 1T-FeFET nonvolatile AND memory array is experimentally investigated for ${V}_{W}$ /2 and ${V}_{W}$ /3 inhibition bias schemes to determine the worst-case memory sensing condition. Read margin analysis reveals that the increased leakage current in the low- ${V}_{\textsf {TH}}$ erased state and the increased read current of the high- ${V}_{\textsf {TH}}$ programmed state are the key factors that limit the maximum array size. [ABSTRACT FROM AUTHOR]

Battery-less IoT devices powered through energy harvesting face a fundamental imbalance between the potential volume of collected data and the amount of energy available for processing that data locally. We explore a combination of approximate computing and intermittent computing-incidental approximate architecture to suit nonvolatile processors (NVPs). [ABSTRACT FROM AUTHOR]

Nonvolatile processors (NVPs) have integrated nonvolatile memory to preserve task-intermediate on-chip state during power emergencies. NVPs hide data backup and restoration from the executing software to provide an execution mode that will always eventually complete the current task. NVPs are emerging as a promising solution for energy-harvesting scenarios, in which the available power supply is unstable and intermittent, because of their ability to ensure that even short periods of sufficient power, on the order of tens of instructions, will result in net forward progress. This article explores the design space for an NVP across different architectures, input power sources, and policies for maximizing forward progress in a framework calibrated using measured results from a fabricated NVP. The authors propose a heterogeneous microarchitecture solution that more efficiently capitalizes on ephemeral power surpluses. [ABSTRACT FROM PUBLISHER]

With the advent of the era of trillion sensors, solar-powered sensor nodes are widely used as they do not require battery charging or replacement. However, the limited and intermittent solar energy supply seriously affects deadline miss rate (DMR) of tasks. Furthermore, traditional solar-powered sensor nodes also suffer from energy loss of battery charging and voltage conversion. Recently, a storage-less and converter-less power supply architecture has been proposed to achieve higher energy efficiency by removing the leaky energy storage and dc voltage conversion. Without energy storages, a node using inter-task scheduling is more sensitive to solar variations, which results in high DMRs. This paper proposes an intra-task scheduling scheme for the storage-less and converter-less solar-powered sensor nodes, whose features include power prediction based on classified solar profiles, a trigger mechanism to select scheduling points, an artificial neural network to calculate task priorities and a fine-grained task selection algorithm. Experimental results show that the proposed algorithm reduces DMR by up to 30% and improves energy utilization efficiency by 20% with trivial energy overheads. [ABSTRACT FROM AUTHOR]

This article provides insights into the design of nonvolatile processors (NVPs) for batteryless applications in the Internet of Things (IoT), in which ambient energy-harvesting techniques provide the power. Achieving reliable, continuous, forward computation with an unstable, intermittent power supply motivates the transition from conventional volatile processors to emerging NVPs. The authors discuss the various design factors and tradeoffs involved in optimizing this forward progress. This article provides a guide for future IoT applications, revealing inherent features of energy-harvesting NVP design. [ABSTRACT FROM PUBLISHER]