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Understanding the dynamics and functionality of the human brain and its relationship with different physical entities has proven to be extremely useful in many applications including disability therapy and designing the next-generation user-interfaces. Communication between the brain and external hardware using neural stimulation and recordings has also been demonstrated recently. Such systems are usually analyzed by employing the brain–machine–body interface (BMBI) model. However, owing to the high complexity of the human brain activity, modeling and analyzing the neural-signals is a resource-intensive task. Moreover, coupling neural signals from different physical entities inevitably leads to large input data sets and hence, also making it data- and computationally intensive. Hence, here we employ a spatiotemporal fractal parallel algorithm to efficiently generate and analyze the BMBI models. However, such an algorithm can lead to demanding on-chip traffic patterns requiring an efficient communication infrastructure among different computing cores. To address this issue, we propose a machine-learning-inspired wireless network-on-chip (WiNoC)-based manycore architecture for handling the compute- and communication-intensive nature of the BMBI applications. The experimental results show that, compared with the traditional wireline mesh NoC, WiNoC achieves up to 55% savings in energy delay product for a system size of 1024 cores. [ABSTRACT FROM AUTHOR]

Recently, a new approach has been introduced that leverages and over-provisions energy storage devices (ESDs) in data centers for performing power capping and facilitating capex/opex reductions, without performance overhead. To fully realize the potential benefits of the hierarchical ESD structure, we propose a comprehensive design, control, and provisioning framework including (i) designing power delivery architecture supporting hierarchical ESD structure and hybrid ESDs for some levels, as well as (ii) control and provisioning of the hierarchical ESD structure including run-time ESD charging/discharging control and design-time determination of ESD types, homogeneous/hybrid options, ESD provisioning at each level. Experiments have been conducted using real Google data center workloads based on realistic data center specifications. [ABSTRACT FROM AUTHOR]

Understanding the role of competition and cooperation among multiple interacting species of microorganisms that constitute the microbiome and decipher how they enforce homeostasis or trigger diseases requires the development of multi-scale computational models capable of capturing both intra-cell processing (i.e., gene-to-protein interactions) and inter-cell interactions. The multi-scale interdependency that governs the interactions from genes to proteins within a cell and from molecular messengers to cells to microbial communities within the environment raises numerous computation and communication challenges. Internal cell processing cannot be simulated without knowledge of the surroundings. Similarly, cell-cell communication cannot be fully abstracted without stated of internal processing and diffusion effects of molecular messengers. To address the compute- and communication-intensive nature of modeling microbial communities, in this paper, we propose a novel reconfigurable NoC-based manycore architecture capable of simulating a large scale microbial community. The reconfiguration of the NoC topology is achieved through the fractal analysis of NoC traffic and use of the on-chip wireless interfaces. More precisely, we analyze the computational and communication workloads and exploit the observed fractal characteristics for proposing a mathematical strategy for NoC reconfiguration. Experimental results demonstrate that the proposed NoC architecture achieves 56.6 and 62.8 percent improvement in energy delay product over the conventional wireline mesh and flatten butterfly-based high radix NoC architectures, respectively. [ABSTRACT FROM AUTHOR]

Networks-on-chip (NoCs) have recently emerged as a scalable alternative to classical bus and point-to-point architectures. To date, performance evaluation of NoC designs is largely based on simulation which, besides being extremely slow, provides little insight on how different design parameters affect the actual network performance. Therefore, it is practically impossible to use simulation for optimization purposes. In this paper, we present a mathematical model for on-chip routers and utilize this new model for NoC performance analysis. The proposed model can be used not only to obtain fast and accurate performance estimates, but also to guide the NoC design process within an optimization loop. The accuracy of our approach and its practical use is illustrated through extensive simulation results. [ABSTRACT FROM AUTHOR]

The article discusses various reports published within the issue, including one on the alternatives to the conventional paradigm of network design, one on designing Network-on-Chip (NoC) architectures under Markovian assumption, and one on the new problems in network design.