40,388 results
Search Results
152. A Self-Adaptive Mutation Neural Architecture Search Algorithm Based on Blocks.
- Author
-
Xue, Yu, Wang, Yankang, Liang, Jiayu, and Slowik, Adam
- Abstract
Recently, convolutional neural networks (CNNs) have achieved great success in the field of artificial intelligence, including speech recognition, image recognition, and natural language processing. CNN architecture plays a key role in CNNs' performance. Most previous CNN architectures are hand-crafted, which requires designers to have rich expert domain knowledge. The trial-and-error process consumes a lot of time and computing resources. To solve this problem, researchers proposed the neural architecture search, which searches CNN architecture automatically, to satisfy different requirements. However, the blindness of the search strategy causes a 'loss of experience' in the early stage of the search process, and ultimately affects the results of the later stage. In this paper, we propose a self-adaptive mutation neural architecture search algorithm based on ResNet blocks and DenseNet blocks. The self-adaptive mutation strategy makes the algorithm adaptively adjust the mutation strategies during the evolution process to achieve better exploration. In addition, the whole search process is fully automatic, and users do not need expert knowledge about CNNs architecture design. In this paper, the proposed algorithm is compared with 17 state-of-the-art algorithms, including manually designed CNN and automatic search algorithms on CIFAR10 and CIFAR100. The results indicate that the proposed algorithm outperforms the competitors in terms of classification performance and consumes fewer computing resources. [ABSTRACT FROM AUTHOR]
- Published
- 2021
- Full Text
- View/download PDF
153. A tale of two directories: implementing distributed shared objects in Java<FN>A preliminary version of this paper appeared in the 1999 Java Grande Conference. ACM Java Grande Conference. A Tale of Two Directories: Implementing Distributed Shared Objects in Java, 1999. </FN>
- Author
-
Herlihy, Maurice and Warres, Michael P.
- Subjects
JAVA programming language ,DISTRIBUTED computing ,COMPUTER networks ,ELECTRONIC data processing ,COMPUTER architecture ,COMPUTER science - Abstract
A directory service keeps track of the location and status of mobile objects in a distributed system. This paper describes our experience implementing two distributed directory protocols as part of the Aleph toolkit, a distributed shared object system implemented in Java. One protocol is a conventional home-based protocol, in which a fixed node keeps track of the object's location and status. The other is a novel Arrow protocol, based on a simple path-reversal algorithm. We were surprised to discover that the Arrow protocol outperformed the home protocol, sometimes substantially, across a range of system sizes. This paper describes a series of experiments testing whether the discrepancy is due to an artifact of the Java run-time system (such as differences in thread management or object serialization costs), or whether it is something inherent in the protocols themselves. In the end, we use insights gained from these experimental results to design a new directory protocol that combines advantages of both. Copyright © 2000 John Wiley & Sons, Ltd. [ABSTRACT FROM AUTHOR]
- Published
- 2000
- Full Text
- View/download PDF
154. The System Architecture and Methods for Efficient Resource-Saving Scheduling in the Fog †.
- Author
-
Klimenko, Anna
- Subjects
COMPUTER architecture ,QUALITY of service ,CLOUD computing ,COMPUTER scheduling ,PROBLEM solving - Abstract
The problem of resource-saving scheduling in a fog environment is considered in this paper. The objective function of the problem in question presupposes the fog nodes' reliability function maximizing. Therefore, to create a schedule, the following is required: the history of the fog devices' state changes and the search space, which consists of preselected nodes of the cloud-fog broker neighbourhood. The obvious approach to providing the scheduler with this information is to poll the fog nodes, yet this can consume the unacceptable time because of the QoS requirements. In this paper, the system architecture and general methods for efficient resource-saving scheduling is presented. The system is based on distributed ledger element usage, which provides the nodes with the proper awareness about the surroundings. The usage of the distributed ledger allows not only for the creation of the resource-saving schedule but also the reduction of the scheduling problem-solving time, which frees addition time that can be used for the solving of user tasks. The latter also affects the overall resource-saving via reliability. The novelty of this paper consists in the development of the hybrid ledger-based system, which integrates and arranges the elements of various ledger types to solve the newly formulated problem. [ABSTRACT FROM AUTHOR]
- Published
- 2023
- Full Text
- View/download PDF
155. Call for Papers.
- Subjects
- *
COMPUTER architecture , *CONFERENCES & conventions - Abstract
Prospective authors are requested to submit new, unpublished manuscripts for inclusion in the upcoming event described in this call for papers. [ABSTRACT FROM PUBLISHER]
- Published
- 2015
- Full Text
- View/download PDF
156. Job Scheduling Strategies for Parallel Processing : 21st International Workshop, JSSPP 2017, Orlando, FL, USA, June 2, 2017, Revised Selected Papers
- Author
-
Dalibor Klusáček, Walfredo Cirne, Narayan Desai, Dalibor Klusáček, Walfredo Cirne, and Narayan Desai
- Subjects
- Software engineering, Computer systems, Computers, Special purpose, Microprocessors, Computer architecture, Logic design
- Abstract
This book constitutes the thoroughly refereed post-conference proceedings of the 21st International Workshop on Job Scheduling Strategies for Parallel Processing, JSSPP 2017, held in Orlando, FL, USA, in June 2017.The 10 revised full papers presented in this book were carefully reviewed and selected from 20 submissions. The papers cover topics in the fields of design and evaluation of new scheduling approaches; performance evaluation of scheduling approaches; workloads; consideration of additional constraints in scheduling systems; scaling and composition of very large scheduling systems; cloud provider issues; interaction between schedulers on different levels; interaction between applications/workloads; experience reports from production systems or large scale compute campaigns.
- Published
- 2018
157. OpenSHMEM and Related Technologies. Big Compute and Big Data Convergence : 4th Workshop, OpenSHMEM 2017, Annapolis, MD, USA, August 7-9, 2017, Revised Selected Papers
- Author
-
Manjunath Gorentla Venkata, Neena Imam, Swaroop Pophale, Manjunath Gorentla Venkata, Neena Imam, and Swaroop Pophale
- Subjects
- Software engineering, Computer programming, Computer hardware description languages, Logic design, Microprocessors, Computer architecture, Computers, Special purpose
- Abstract
This book constitutes the proceedings of the 4th OpenSHMEM Workshop, held in Annapolis, MD, USA, in August 2017.The 11 full papers presented in this book were carefully reviewed and selected from 14 submissions. The papers discuss a variety of ideas for extending the OpenSHMEM specification and making it efficient for current and next generation systems. This includes new research for communication contexts in OpenSHMEM, different optimizations for OpenSHMEM on shared memory machines, exploring the implementation of OpenSHMEM and its memory model on Intel's KNL architecture, and implementing new applications and benchmarks with OpenSHMEM.
- Published
- 2018
158. Parallel Computational Technologies : 12th International Conference, PCT 2018, Rostov-on-Don, Russia, April 2–6, 2018, Revised Selected Papers
- Author
-
Leonid Sokolinsky, Mikhail Zymbler, Leonid Sokolinsky, and Mikhail Zymbler
- Subjects
- Computer systems, Computers, Special purpose, Microprocessors, Computer architecture, Operating systems (Computers), Logic design, Computer science—Mathematics
- Abstract
This book constitutes the refereed proceedings of the 12th International Conference on Parallel Computational Technologies, PCT 2018, held in Rostov-on-Don, Russia, in April 2018.The 24 revised full papers presented were carefully reviewed and selected from 167 submissions. The papers are organized in topical sections on high performance architectures, tools and technologies; parallel numerical algorithms; supercomputer simulation.
- Published
- 2018
159. Conference Calendar.
- Author
-
Craeynest, Dirk
- Subjects
SOFTWARE verification ,SOFTWARE architecture ,HIGH performance computing ,COMPUTER science conferences ,REAL-time computing ,COMPUTER architecture ,DISTRIBUTED computing - Published
- 2022
160. Architecture Definition and Evaluation Technical Evaluation Report.
- Author
-
Vant, Malcolm R.
- Subjects
CONFERENCES & conventions ,COMPUTER architecture ,ARCHITECTURAL models ,COST control ,CLOUD computing - Abstract
The CSO-IST-115 symposium on Architecture Definition and Evaluation was held in Toulouse, France May 13-14, 2013. The symposium addressed several key areas in the use and development of Architectural Frameworks such as the NAF (NATO Architectural Framework) and its associated standards DODAF (Department of Defence Architectural Framework), MODAF (Ministry of Defence Architectural Framework) and others. Standard Architectural Frameworks were first introduced by the United States in an effort to cut the costs involved in specifying and then building complex military systems. Other nations, and NATO, quickly saw the benefits and followed suit. Any of these frameworks provide a common set of viewpoints and way of describing systems of systems. Although they are similar, the frameworks are not the same, and in some cases their underpinning meta-models differ. Differences among them cause difficulties when assembling multinational Command Support Systems, such as the Afghanistan Mission Network. Furthermore, there is no specified methodology associated with the frameworks, and therefore there can be a steep learning curve when adopting them since each developer tends to develop their own methodology and adopt their own toolsets. This diversity of approach and lack of specified methods leads to a lack of interoperability among developers and a reduction in possible productivity. Other issues exist such as the difficulty in dealing with real-time or dynamic situations in some of the frameworks. The symposium covered various aspects of the use of architecture frameworks such as lessons learned, model-based approaches to development, methodologies for executable architecture, dealing with dynamics, re-engineering legacy systems and cloud architectures. During the Symposium, a very strong message came through that a common methodology is sorely needed and that a true single unified architecture framework would be very useful to all the nations. Many other positive lessons learned and successful methods were also discussed. [ABSTRACT FROM AUTHOR]
- Published
- 2013
161. Computer Architectures Empowered by Sierpinski Interconnection Networks utilizing an Optimization Assistant.
- Author
-
Iqbal, Muhammad Waseem and Alshammry, Nizal
- Subjects
COMPUTER architecture ,COMPUTER science ,VERY large scale circuit integration ,COMPUTER engineering ,COMPUTER engineers - Abstract
The current article discusses Sierpinski networks, which are fractal networks with certain applications in computer science, physics, and chemistry. These networks are typically used in complicated frameworks, fractals, and recursive assemblages. The results derived in this study are in mathematical and graphical format for particular classes of these networks of two distinct sorts with two invariants, K-Banhatti Sombor (KBSO) and Dharwad, along with their reduced forms. These results can facilitate the formation, scalability, and introduction of novel interconnection network topologies, chemical compounds, and VLSI processor circuits. The mathematical expressions employed in this research offer modeling insights and design guidelines to computer engineers. The derived simulation results demonstrate the optimal ranges for a certain network. The optimization assistant tool deployed in this work provides a single maximized value representing the maximum optimized network. These ranges can be put into service to dynamically establish a network according to the requirements of this paper. [ABSTRACT FROM AUTHOR]
- Published
- 2024
- Full Text
- View/download PDF
162. Technologies of Data Protection and Institutional Decisions for Data Sovereignty.
- Author
-
Del Re, Enrico
- Subjects
DATA privacy ,DATA protection ,COMPUTER architecture ,SCIENTIFIC literature ,BIOMETRIC identification - Abstract
This paper aims to propose innovative actions of advanced technological solutions and consequent necessary institutional decisions to achieve in a reasonable time the definitive confidential data protection and data sovereignty, based on available scientific results. Confidential data protection is a fundamental and strategic issue in next-generation Internet systems to guarantee data sovereignty and the respect of human rights as stated in the foundation of the United Nations. Even if presently many international regulations are decisive steps to guarantee data protection within normative contexts, they are not adequate to face new technologies, such as facial recognition, automatic profiling, position tracking, biometric data, AI applications, and many others in the future, as they are implemented without any awareness by the interested subjects. Therefore, a new approach to data protection is mandatory based on innovative and disruptive technological solutions. A recent OECD report highlighted the need for the so-called Privacy-Enhancing Technologies (PETs) for the effective protection of confidential data, even more urgent for the coexistence of privacy and data sharing in international contexts. A common feature of these technologies is the use of software methodologies that can run on currently available microprocessors and their present immaturity. More effective and definitive protection can be achieved with another methodological approach based on the paradigm of 'Data Usage Control'. This new concept guarantees data protection policy by default and initial design and it requires a new architecture of the data and a new HW&SW architecture of the computers. This contribution has a two-fold objective: first, to clarify why regulations alone and present technological proposals are not adequate for the effective and definitive protection of data and, second, to indicate the new necessary technological approach and the simultaneous institutional actions required to achieve the definitive protection and sovereignty of data in reasonable times, based on the results already available in the scientific literature. [ABSTRACT FROM AUTHOR]
- Published
- 2024
- Full Text
- View/download PDF
163. Empirical Architectural Analysis on Performance Scalability of Petascale All-Flash Storage Systems.
- Author
-
Ajdari, Mohammadamin, Montazerzohour, Behrang, Abdi, Kimia, and Asadi, Hossein
- Abstract
In this paper, we first analyze a real storage system consisting of 72 SSDs utilizing either Hardware RAID (HW-RAID) or Software RAID (SW-RAID), and show that SW-RAID is up to 7× faster. We then reveal that with an increasing number of SSDs, the limited I/O parallelism in SAS controllers and multi-enclosure handshaking overheads cause a significant performance drop, minimizing the total I/O Per Second (IOPS) of a 144-SSD system to less than a single SSD. Second, we disclose the most important architectural parameters that affect a large-scale storage system. Third, we propose a framework that models a large-scale storage system and estimates the system IOPS and system resource usage for various architectures. We verify our framework against a real system and show its high accuracy. Lastly, we analyze a use case of a 240-SSD system and reveal how our framework guides architects in storage system scaling. [ABSTRACT FROM AUTHOR]
- Published
- 2024
- Full Text
- View/download PDF
164. Exploiting Direct Memory Operands in GPU Instructions.
- Author
-
Mohammadpur-Fard, Ali, Darabi, Sina, Falahati, Hajar, Mahani, Negin, and Sarbazi-Azad, Hamid
- Abstract
GPUs are widely used for diverse applications, particularly data-parallel tasks like machine learning and scientific computing. However, their efficiency is hindered by architectural limitations, inherited from historical RISC processors, in handling memory loads causing high register file contention. We observe that a significant number (around 26%) of values present in the register file are typically used only once, contributing to more than 25% of the total register file bank conflicts, on average. This paper addresses the challenge of single-use memory values in the GPU register file (i.e. data values used only once) which wastes space and increases latency. To this end, we introduce a novel mechanism inspired by CISC architectures. It replaces single-use loads with direct memory operands in arithmetic operations. Our approach improves performance by 20% and reduces energy consumption by 18%, on average, with negligible (<1%) hardware overhead. [ABSTRACT FROM AUTHOR]
- Published
- 2024
- Full Text
- View/download PDF
165. Movement Representation Learning for Pain Level Classification.
- Author
-
Olugbade, Temitayo, Williams, Amanda C de C, Gold, Nicolas, and Bianchi-Berthouze, Nadia
- Abstract
Self-supervised learning has shown value for uncovering informative movement features for human activity recognition. However, there has been minimal exploration of this approach for affect recognition where availability of large labelled datasets is particularly limited. In this paper, we propose a P-STEMR (Parallel Space-Time Encoding Movement Representation) architecture with the aim of addressing this gap and specifically leveraging the higher availability of human activity recognition datasets for pain-level classification. We evaluated and analyzed the architecture using three different datasets across four sets of experiments. We found statistically significant increase in average F1 score to 0.84 for pain level classification with two classes based on the architecture compared with the use of hand-crafted features. This suggests that it is capable of learning movement representations and transferring these from activity recognition based on data captured in lab settings to classification of pain levels with messier real-world data. We further found that the efficacy of transfer between datasets can be undermined by dissimilarities in population groups due to impairments that affect movement behaviour and in motion primitives (e.g. rotation versus flexion). Future work should investigate how the effect of these differences could be minimized so that data from healthy people can be more valuable for transfer learning. [ABSTRACT FROM AUTHOR]
- Published
- 2024
- Full Text
- View/download PDF
166. Enhancing Monitoring Performance: A Microservices Approach to Monitoring with Spyware Techniques and Prediction Models.
- Author
-
Rossetto, Anubis Graciela de Moraes, Noetzold, Darlan, Silva, Luis Augusto, and Leithardt, Valderi Reis Quietinho
- Subjects
COMPUTER architecture ,SPYWARE (Computer software) ,PREDICTION models ,DATA security failures ,COMPUTER monitors ,AUTOMATIC speech recognition - Abstract
In today's digital landscape, organizations face significant challenges, including sensitive data leaks and the proliferation of hate speech, both of which can lead to severe consequences such as financial losses, reputational damage, and psychological impacts on employees. This work considers a comprehensive solution using a microservices architecture to monitor computer usage within organizations effectively. The approach incorporates spyware techniques to capture data from employee computers and a web application for alert management. The system detects data leaks, suspicious behaviors, and hate speech through efficient data capture and predictive modeling. Therefore, this paper presents a comparative performance analysis between Spring Boot and Quarkus, focusing on objective metrics and quantitative statistics. By utilizing recognized tools and benchmarks in the computer science community, the study provides an in-depth understanding of the performance differences between these two platforms. The implementation of Quarkus over Spring Boot demonstrated substantial improvements: memory usage was reduced by up to 80% and CPU usage by 95%, and system uptime decreased by 119%. This solution offers a robust framework for enhancing organizational security and mitigating potential threats through proactive monitoring and predictive analysis while also guiding developers and software architects in making informed technological choices. [ABSTRACT FROM AUTHOR]
- Published
- 2024
- Full Text
- View/download PDF
167. BlockGraph: a scalable secure distributed ledger that exploits locality.
- Author
-
Goldstein, Seth Copen, Gao, Sixiang, and Sun, Zhenbo
- Subjects
BLOCKCHAINS ,COMPUTER architecture ,CRYPTOCURRENCIES ,BITCOIN ,TRANSACTION costs ,SCALABILITY - Abstract
Distributed public ledgers, the key to modern cryptocurrencies and the heart of many novel applications, have scalability problems. Ledgers such as the blockchain underlying Bitcoin can process fewer than 10 transactions per second (TPS). The cost of transactions is high, and the time to confirm a transaction is in the minutes. We present the BlockGraph, a scalable distributed public ledger inspired by principles of computer architecture. The BlockGraph exploits the natural locality of transactions to allow publishing independent transactions in parallel. It extends the blockchain with three new transactions to create a unified consistent ledger out of essentially independent blockchains. The most important change is the introduction of the blockstamp transaction, which essentially checkpoints a local blockchain and secures it against attack. The result is a locality-based, simple, secure, sharding protocol which keeps all transactions readable. This paper introduces the BlockGraph protocol, proves that it is consistent and can achieve many thousands of TPS. Using our implementation (a small extension to Bitcoin core) we demonstrate that it, in practice, can significantly improve throughput. [ABSTRACT FROM AUTHOR]
- Published
- 2024
- Full Text
- View/download PDF
168. Gender determination from periocular images using deep learning based EfficientNet architecture.
- Author
-
Nambiar, Viji B, Ramamurthy, Bojan, and Veeresha, Pundikala
- Subjects
CONVOLUTIONAL neural networks ,DEEP learning ,COMPUTER architecture ,LANGUAGE models ,MATHEMATICAL functions - Abstract
In this study, we obtain a sex prediction algorithm based on CNN in two ways - building a red Convolutional Neural Network (CNN) model from scratch and via transfer learning. We built a model from scratch and compared it with fine-tuned EfficientNetB1. We use these models for gender determination using periocular images and compare the two models depending on the accuracy of the models. The CNN model proposed from scratch yields an accuracy of 94.46% while the fine-tuned EfficientNetB1 yields an accuracy of 97.94%. This paper is one of the first works in determining gender from periocular images in the visible spectrum using a CNN model built from the outset. [ABSTRACT FROM AUTHOR]
- Published
- 2024
- Full Text
- View/download PDF
169. The Impact of Emerging Technologies on Architectures and System-level Management: Invited Paper
- Author
-
Hsiang-Yun Cheng, Jorg Henkel, Dayane Reis, Xunzhao Yin, Martin Rapp, Chia-Lin Yang, Michael Niemier, Cheng Zhuo, Hussam Amrouch, Sami Salamin, X. Sharon Hu, and Di Gao
- Subjects
010302 applied physics ,Emerging technologies ,Computer science ,Transistor ,Context (language use) ,02 engineering and technology ,01 natural sciences ,020202 computer hardware & architecture ,Resistive random-access memory ,law.invention ,symbols.namesake ,CMOS ,Computer architecture ,law ,0103 physical sciences ,0202 electrical engineering, electronic engineering, information engineering ,Key (cryptography) ,symbols ,Von Neumann architecture - Abstract
The goal of this work is to introduce and discuss different kinds of emerging technologies for logic circuitry and memory with respect to the key question of how they will impact future system-on-chip architectures and system-level management techniques. It is obvious that emerging technologies should have an impact there in order to fully exploit their technological advantages but also in order to deal with any disadvantages they might come with. In this special session paper, three promising emerging technologies are presented: (i) Negative Capacitance Field-Effect Transistor (NCFET) as a new CMOS technology with advantages primarily for low-power design, (ii) Ferroelectric FET (FeFET) as a non-volatile, area-efficient and low-power combined logic and memory as well as (iii) a Phase-Change Memory (PCM) and Resistive RAM (ReRAM) offering a large potential for tackling the memory wall problem in the von Neumann architecture. Our analysis demonstrates that not only new computing paradigms are promoted by these new technologies, it will also be seen that the trade-offs between the classical design parameters of low power, performance etc. will shift and hence emerging technologies will offer new Pareto points in the design space of future on-chip architectures. In that context, this work is unique as it bridges the gap between the technology side and system/architecture-level side to draw a vision of new technologies and their impact on architectures and system-level management.
170. Lazy type inference for the strictness analysis of lists
- Author
-
Hankin, Chris, Le Métayer, Daniel, Goos, G., editor, Hartmanis, J., editor, and Sannella, Donald, editor
- Published
- 1994
- Full Text
- View/download PDF
171. Top Picks in Computer Architecture from Conferences in 2018.
- Author
-
Dwarkadas, Sandhya
- Subjects
COMPUTER architecture ,ORDER picking systems ,MESSAGE authentication codes ,PARALLEL computers ,RANDOM access memory - Published
- 2019
- Full Text
- View/download PDF
172. Online Policies for Energy Harvesting Receivers With Time-Switching Architectures.
- Author
-
Ni, Zhengwei and Motani, Mehul
- Abstract
In the real-world, it is virtually impossible to have non-causal knowledge of future events. Research in energy harvesting (EH) systems that assumes knowledge of future energy arrivals falls short in terms of practical utility, pointing to the need for online strategies. In addition, the modeling and analysis for EH transmitter and receiver are inherently different. Compared with EH transmitter, EH receiver has received less attention. In this paper, we formulate Markov decision process problems and perform online optimization to maximize the number of bits decoded for an EH receiver with a time-switching architecture, which harvests energy from both a dedicated transmitter and other sources. We consider both infinite and finite horizon scenarios. For the infinite horizon, we provide an upper bound on the average expected reward. Then, we find an optimal policy which can achieve performance arbitrarily close to this bound. For the finite horizon, we first provide a policy obtained from standard backward induction with space quantization. Its performance can be close to optimal online performance as the number of quantization intervals increases, at the cost of relatively high computational complexity. Then, by carefully restricting the state space, we present a computationally efficient policy, which achieves comparatively good performance. [ABSTRACT FROM AUTHOR]
- Published
- 2019
- Full Text
- View/download PDF
173. High Performance Computing : ISC High Performance Digital 2021 International Workshops, Frankfurt Am Main, Germany, June 24 – July 2, 2021, Revised Selected Papers
- Author
-
Heike Jagode, Hartwig Anzt, Hatem Ltaief, Piotr Luszczek, Heike Jagode, Hartwig Anzt, Hatem Ltaief, and Piotr Luszczek
- Subjects
- Computer engineering, Computer networks, Logic design, Microprocessors, Computer architecture, Artificial intelligence, Application software
- Abstract
This book constitutes the refereed post-conference proceedings of 9 workshops held at the 35th International ISC High Performance 2021 Conference, in Frankfurt, Germany, in June-July 2021:Second International Workshop on the Application of Machine Learning Techniques to Computational Fluid Dynamics and Solid Mechanics Simulations and Analysis; HPC-IODC: HPC I/O in the Data Center Workshop; Compiler-assisted Correctness Checking and Performance Optimization for HPC; Machine Learning on HPC Systems;4th International Workshop on Interoperability of Supercomputing and Cloud Technologies;2nd International Workshop on Monitoring and Operational Data Analytics;16th Workshop on Virtualization in High-Performance Cloud Computing; Deep Learning on Supercomputers; 5th International Workshop on In Situ Visualization. The 35 papers included in this volume were carefully reviewed and selected. They cover all aspects of research, development, and application of large-scale,high performance experimental and commercial systems. Topics include high-performance computing (HPC), computer architecture and hardware, programming models, system software, performance analysis and modeling, compiler analysis and optimization techniques, software sustainability, scientific applications, deep learning.Chapter “Machine-Learning-Based Control of Perturbed and Heated Channel Flows” is available open access under a Creative Commons Attribution 4.0 International License via link.springer.com.
- Published
- 2021
174. Foreword to TODS Invited Papers Issue 2011.
- Author
-
ÖZSOYOĞLU, Z. MERAL
- Subjects
- *
COMPUTER architecture , *DATABASES - Abstract
An introduction is presented which discusses various reports published within the journal including "Finding Maximal Cliques in Massive Networks," "Designing Fast Architecture-Sensitive Tree Search on Modern Multicore/Many-Core Processors," and "Characterizing Schema Mappings via Data Examples."
- Published
- 2011
175. Multi-Layer Faults in the Architectures of Mobile, Context-Aware Adaptive Applications: A Position Paper.
- Author
-
Sama, Michele, Rosenblum, David S., Zhimin Wang, and Elbaum, Sebastian
- Subjects
CELL phones ,COMPUTER software ,COMPUTER architecture ,DETECTORS ,TELEPHONES - Abstract
Five cellphones are sold every second, and there are four times more cellphones than computers, meaning there are some billions of mobile handheld devices in existence. Modern cellphones are equipped with multiple context sensors used by increasingly sophisticated software applications that exploit the sensors, allowing the applications to adapt automatically to changes in the surrounding environment, such as by responding to the location and speed of the user. The architecture of such applications is typically layered and incorporates a context-awareness middleware to support processing of context values. While this layered architecture is very natural for the design and implementation of applications, it gives rise to new kinds of faults and faulty behavior modes, which are difficult to detect using existing validation techniques. In this paper we provide scenarios illustrating such faults and exploring how they manifest in context-aware adaptive applications. [ABSTRACT FROM AUTHOR]
- Published
- 2008
176. VLSI Design and Test : 21st International Symposium, VDAT 2017, Roorkee, India, June 29 – July 2, 2017, Revised Selected Papers
- Author
-
Brajesh Kumar Kaushik, Sudeb Dasgupta, Virendra Singh, Brajesh Kumar Kaushik, Sudeb Dasgupta, and Virendra Singh
- Subjects
- Computers, Microprocessors, Computer architecture, Computer networks
- Abstract
This book constitutes the refereed proceedings of the 21st International Symposium on VLSI Design and Test, VDAT 2017, held in Roorkee, India, in June/July 2017. The 48 full papers presented together with 27 short papers were carefully reviewed and selected from 246 submissions. The papers were organized in topical sections named: digital design; analog/mixed signal; VLSI testing; devices and technology; VLSI architectures; emerging technologies and memory; system design; low power design and test; RF circuits; architecture and CAD; and design verification.
- Published
- 2017
177. Languages and Compilers for Parallel Computing : 29th International Workshop, LCPC 2016, Rochester, NY, USA, September 28-30, 2016, Revised Papers
- Author
-
Chen Ding, John Criswell, Peng Wu, Chen Ding, John Criswell, and Peng Wu
- Subjects
- Compilers (Computer programs), Computer systems, Computer programming, Software engineering, Operating systems (Computers), Microprocessors, Computer architecture
- Abstract
This book constitutes the thoroughly refereed post-conference proceedings of the 29th International Workshop on Languages and Compilers for Parallel Computing, LCPC 2016, held in Rochester, NY, USA, in September 2016. The 20 revised full papers presented together with 4 short papers were carefully reviewed. The papers are organized in topical sections on large scale parallelism, resilience and persistence, compiler analysis and optimization, dynamic computation and languages, GPUs and private memory, and runt-time and performance analysis.
- Published
- 2017
178. Call for Papers.
- Subjects
- *
DEADLINES , *MANUSCRIPTS , *SOFTWARE-defined networking , *INTERNET security , *COMPUTER architecture - Abstract
The article discusses deadlines for submission of manuscript of periodical on various topics related to architectures, algorithms and applications of software defined vehicular networks (SDVN). Topics discussed include security and privacy in SDVN; data offloading in SDVN and flexible architecture in SDVN.
- Published
- 2016
- Full Text
- View/download PDF
179. VLSI Processor Design Methodology* *The MIPS processor design, which is used as an example in this paper, has been supported by the Defense Advanced Research Projects Agency under grants MDA903-79-C-680 and MDA903-83-C-0335
- Author
-
John L. Hennessy and Steven A. Przybylski
- Subjects
Very-large-scale integration ,Computer science ,business.industry ,Interface (computing) ,Processor design ,Transistor ,Integrated circuit ,law.invention ,Computer architecture ,law ,System integration ,Architecture ,business ,Host (network) - Abstract
Publisher Summary Integrated Circuit (IC) technology has made the production of chips with several transistors possible. Systems of such complexity are difficult to design. The computer architect faces problems in the areas of system partitioning with sub goal specification, subsystems interface specification and verification, and overall system integration. This improvement in IC technology allows the fabrication of processors with complexity, comparable to the largest mainframe computers designed using off-the-shelf technologies (SSI, MSI, and LSI). The advent of very large scale integrated (VLSI) processor has significantly changed the way in which computers are designed and implemented. This chapter discusses the use of VLSI as an implementation medium and it focuses on the design of general purpose microprocessors. In many ways, the architecture and organization of a VLSI processor are similar to the designs used in the CPUs of modern machines implemented by using standard parts. The MOS technology imposes some new constraints that emphasize on the interaction between architecture and implementation. The chapter discusses the issues that arise in determining the suitability of architecture as a program host, the implications of the architecture on the organization, and some guidelines to help evaluate the suitability of architecture both for an application environment and for implementation using VLSI.
- Published
- 1986
180. Event‐based high throughput computing: A series of case studies on a massively parallel softcore machine.
- Author
-
Vousden, Mark, Morris, Jordan, McLachlan Bragg, Graeme, Beaumont, Jonathan, Rafiev, Ashur, Luk, Wayne, Thomas, David, and Brown, Andrew
- Subjects
CONDENSED matter physics ,ELECTRICITY pricing ,COMPUTATIONAL chemistry ,COMPUTER architecture ,MESSAGE passing (Computer science) - Abstract
This paper introduces an event‐based computing paradigm, where workers only perform computation in response to external stimuli (events). This approach is best employed on hardware with many thousands of smaller compute cores with a fast, low‐latency interconnect, as opposed to traditional computers with fewer and faster cores. Event‐based computing is timely because it provides an alternative to traditional big computing, which suffers from immense infrastructural and power costs. This paper presents four case study applications, where an event‐based computing approach finds solutions to orders of magnitude more quickly than the equivalent traditional big compute approach, including problems in computational chemistry and condensed matter physics. [ABSTRACT FROM AUTHOR]
- Published
- 2023
- Full Text
- View/download PDF
181. A countless variant simulation-based toolkit for remote learning and evaluation.
- Author
-
Romero, Felipe, Bandera, Gerardo, Romero, Javier, and Romero, Luis F.
- Subjects
DISTANCE education ,COMPUTER architecture ,COVID-19 pandemic ,EDUCATORS ,ACADEMIC motivation - Abstract
The COVID-19 pandemic has brought about a profound transformation in the educational landscape in recent months. Educators worldwide have been challenged to tackle academic issues they could never have imagined. Among the most stressful situations faced by students and teachers is implementing online assessments. This paper proposes a system that includes exam prototypes for computer architecture modules at the higher education level. This system generates a wide range of questions and variations on the server side, supported by a set of simulators, resulting in many unique examination proposals. This system streamlines the monitoring process for the teacher, as it eliminates the possibility of two students receiving similar exams and reduces student stress by allowing them to practice with a limitless number of exam samples. This paper also highlights several indicators that demonstrate the advantages of this framework. [ABSTRACT FROM AUTHOR]
- Published
- 2023
- Full Text
- View/download PDF
182. A Novel Architecture Based on Business Intelligence Approach to Exploit Big Data.
- Author
-
Nejad, M. R. Behbahani and Rashid, H.
- Subjects
BIG data ,BUSINESS intelligence ,DECISION making ,UNIFIED modeling language ,COMPUTER architecture - Abstract
Background and Objectives: Big data is a combination of structured, semi-structured and unstructured data collected by organizations that must be stored and used for decision-making. Businesses that deal with the business intelligence system, as well as their data sources, have a major challenge in exploiting Big Data. The current architecture of business intelligence systems is not capable of incorporating and exploiting Big Data. In this paper, an architecture is developed to respond to this challenge. Methods: This paper focuses on the promotion of business intelligence to create an ability to exploit Big Data in business intelligence. In this regard, a new architecture is proposed to integrate both Business Intelligence and Big Data architectures. To evaluate the proposed architecture, we investigated business intelligence architecture and Big Data architecture. Then, we developed a Unified Modeling Language diagram for the proposed architecture. In addition, using the Colored Petri-Net, the proposed architecture is evaluated in a case study. Results: The results show that our architectural system has a higher efficiency in performing all steps, average time, and maximum time compared to business intelligence architecture. Conclusion: The proposed architecture can help companies and organizations gain more value from their data sources and better support managers and organizations in their decision-making. [ABSTRACT FROM AUTHOR]
- Published
- 2023
- Full Text
- View/download PDF
183. Fault Isolation on Request Based on Decentralized Residual Generation.
- Author
-
Chanthery, Elodie, Trave-Massuyes, Louise, and Indra, Saurabh
- Subjects
FAULT tolerance (Engineering) ,ORBITS (Astronomy) ,AUTOMATIC control systems - Abstract
This paper presents the theoretical keystone for a decentralization of model-based diagnosis by proving the equivalence between decentralized and centralized residual generation. The proof is based on structural analysis and graph-theoretical concepts. The second contribution of this paper is the design of a decentralized fault-focused residual generation scheme advantageously implementing a strategy of fault isolation on request. Algorithms are tested on the attitude determination and control system of a low Earth orbit satellite. [ABSTRACT FROM PUBLISHER]
- Published
- 2016
- Full Text
- View/download PDF
184. Speculative Taint Tracking (STT): A Comprehensive Protection for Speculatively Accessed Data.
- Author
-
Jiyong Yu, Mengjia Yan, Khyzha, Artem, Morrison, Adam, Torrellas, Josep, and Fletcher, Christopher W.
- Subjects
COMPUTER security ,DATA protection ,MALWARE prevention ,COMPUTER architecture ,COMPUTER performance - Abstract
Speculative execution attacks present an enormous security threat, capable of reading arbitrary program data under malicious speculation, and later exfiltrating that data over microarchitectural covert channels. This paper proposes speculative taint tracking (STT), a high security and high performance hardware mechanism to block these attacks. The main idea is that it is safe to execute and selectively forward the results of speculative instructions that read secrets, as long as we can prove that the forwarded results do not reach potential covert channels. The technical core of the paper is a new abstraction to help identify all microarchitectural covert channels, and an architecture to quickly identify when a covert channel is no longer a threat. We further conduct a detailed formal analysis on the scheme in a companion document. When evaluated on SPEC06 workloads, STT incurs 8.5% or 14.5% performance overhead relative to an insecure machine. [ABSTRACT FROM AUTHOR]
- Published
- 2021
- Full Text
- View/download PDF
185. Editorial.
- Author
-
Ha, Soonhoi and Eles, Petru
- Subjects
EMBEDDED computer systems ,COMPUTER architecture ,SOFTWARE architecture - Abstract
This large volume of special issue includes all regular papers presented at Embedded Systems Week (ESWEEK) 2018 that brings together three leading conferences (CASES, CODES+ISSS, and EMSOFT) in the embedded systems area. ESWEEK is a unique premier event that covers all aspects of embedded systems design and hardware/software architectures. ESWEEK presents a wide range of topics unveiling state-of-the-art techniques as can be found in this special issue. Following the journal-integrated publication model started last year, the three conferences conducted the journal-like two-stage peer-reviewed process before final decision. Acceptance rates have been about 25.5% for all conferences with a total number of 270 submissions to the journal track. [ABSTRACT FROM AUTHOR]
- Published
- 2018
- Full Text
- View/download PDF
186. One-Step Calculation Circuit of FFT and Its Application.
- Author
-
Liu, Yiyang, Wang, Chunhua, Sun, Jingru, Du, Sichun, and Hong, Qinghui
- Subjects
DISCRETE Fourier transforms ,FAST Fourier transforms ,ANALOG circuits ,SIGNAL processing - Abstract
Discrete Fourier Transform (DFT) and Fast Fourier Transform (FFT) are core components in the field of signal processing. However, in the existing research, there is no fully analog circuit that can realize the one-step calculation of FFT. Therefore, in this paper, an analog circuit that can calculate FFT and its inverse transform IFFT in one-step is proposed. First, a circuit that can realize complex number operations is designed. On the basis of this structure, a fully analog circuit that can realize fast and efficient computing of FFT and IFFT in one-step is proposed. In addition, different coefficient matching can be obtained to achieve arbitrary points of FFT and IFFT by adjusting the resistance value of the memristor, which has good programmability. Specific examples are given in the paper to evaluate the proposed method. The PSPICE simulation results show that the average accuracy is above 99.98%. More importantly, the calculation speed has been greatly improved compared with MATLAB simulation. Finally, the proposed circuit can be used to quickly solve convolution operation, and the average accuracy can reach 99.95%. [ABSTRACT FROM AUTHOR]
- Published
- 2022
- Full Text
- View/download PDF
187. Top Picks from the 2013 Computer Architecture Conferences.
- Author
-
Thottethodi, Mithuna S. and Mukherjee, Shubu
- Subjects
COMPUTER architecture ,COMPUTER input-output equipment ,SYSTEMS development ,COMPUTER systems ,COMPUTER engineering ,CONFERENCES & conventions - Abstract
This special issue is the eleventh in an important tradition in the computer architecture community: IEEE Micro's Top Picks from the Computer Architecture Conferences. This tradition provides a means for sharing a sample of the best papers published in computer architecture in 2013 with the IEEE Micro readership and researchers in the computer architecture community. [ABSTRACT FROM AUTHOR]
- Published
- 2014
- Full Text
- View/download PDF
188. Implementation of Efficient Vedic Multiplier and Its Performance Evaluation.
- Author
-
Mugatkar, Ashutosh and Gajre, Suhas S.
- Subjects
INTEGRATED circuits ,COMPUTER architecture ,MULTIPLIERS (Mathematical analysis) ,MULTIPLICATION ,MATHEMATICS - Abstract
The ancient Vedic mathematics is well known for quicker handy multiplications but its recognition as an integrated circuit core against existing hardware multipliers is not established. As optimized hardware implementation of binary multiplier is one of the prominent unsolved problems in computer architecture, this paper proposes efficient Urdhava Tiryakbhyam Vedic multiplier architecture and compares it with the set of hierarchical multiplication algorithms which generate multiplication result in a single clock cycle. Two innovative algorithms are proposed here, one with a compact structure and another for faster execution. Also, its optimized transistor level layout is designed and implemented. To maintain homogeneity for comparison, all the algorithms are programmed on a common HDL language platform and analyzed with the same tool and technology. Final results indicate that the proposed architecture delivers 15.5% less power delay product (PDP) compared to closest competitor algorithm. [ABSTRACT FROM AUTHOR]
- Published
- 2023
- Full Text
- View/download PDF
189. Guest Editorial: Special Issue on ACCV 2018.
- Author
-
Jawahar, C. V., Li, Hongdong, Mori, Greg, and Schindler, Konrad
- Subjects
COMPUTER architecture ,HOSPITALITY ,COMPUTER vision ,DEEP learning - Abstract
This special issue consists of papers ranging from both classical multi-view geometry to recent deep learning methods deep stereo matching networks, GAN and adversarial learning, and multi-task learning for video object segmentation. The idea for a special issue about architectures and theories for computer vision came from the ACCV conference held in 2018. We, the program chairs of ACCV 2018 and guest editors of this special issue, invited the authors of the ACCV'18 award-winning papers to submit extended manuscripts to this special issue. [Extracted from the article]
- Published
- 2020
- Full Text
- View/download PDF
190. CMOS interface with biological molecules and cells - Invited review paper
- Author
-
Tianyang Ye, Hongkun Park, Jeffrey Abbott, and Donhee Ham
- Subjects
010302 applied physics ,chemistry.chemical_classification ,Computer science ,business.industry ,Computation ,Biomolecule ,Interface (computing) ,Big data ,02 engineering and technology ,Integrated circuit ,021001 nanoscience & nanotechnology ,01 natural sciences ,law.invention ,CMOS ,chemistry ,Computer architecture ,Hardware_GENERAL ,law ,0103 physical sciences ,Scalability ,Hardware_INTEGRATEDCIRCUITS ,0210 nano-technology ,business - Abstract
CMOS technology and its Moore’s Law scaling is an enormously successful technology paradigm that has continued to transform our computation and communication abilities. Outside the applications in computation and communication, CMOS technology has been increasingly applied to the life sciences, with a wealth of silicon integrated circuits developed to interface with biological molecules and cells. Concretely, large-scale arrays of active electrodes are integrated using CMOS technology for highly parallel electronic detection of biomolecular/ionic charges and cellular potentials for DNA sequencing, molecular diagnostics, and electrophysiology. Parallelism enabled by CMOS scalability is well suited to process the big data in these biotechnological applications. Here we offer a brief review on these CMOS-bio interfaces, while the corresponding presentation will focus on a sub-topic of CMOS electrophysiology with mammalian neurons.
191. High Performance Computing : ISC High Performance 2016 International Workshops, ExaComm, E-MuCoCoS, HPC-IODC, IXPUG, IWOPH, P^3MA, VHPC, WOPSSS, Frankfurt, Germany, June 19–23, 2016, Revised Selected Papers
- Author
-
Michela Taufer, Bernd Mohr, Julian M. Kunkel, Michela Taufer, Bernd Mohr, and Julian M. Kunkel
- Subjects
- Electronic digital computers—Evaluation, Computers, Microprocessors, Computer architecture, Computer science, Application software
- Abstract
This book constitutes revised selected papers from 7 workshops that were held in conjunction with the ISC High Performance 2016 conference in Frankfurt, Germany, in June 2016. The 45 papers presented in this volume were carefully reviewed and selected for inclusion in this book. They stem from the following workshops: Workshop on Exascale Multi/Many Core Computing Systems, E-MuCoCoS; Second International Workshop on Communication Architectures at Extreme Scale, ExaComm; HPC I/O in the Data Center Workshop, HPC-IODC; International Workshop on OpenPOWER for HPC, IWOPH; Workshop on the Application Performance on Intel Xeon Phi – Being Prepared for KNL and Beyond, IXPUG; Workshop on Performance and Scalability of Storage Systems, WOPSSS; and International Workshop on Performance Portable Programming Models for Accelerators, P3MA.
- Published
- 2016
192. Applications, Deployments, and Integration of Internet of Drones (IoD): A Review.
- Author
-
Abualigah, Laith, Diabat, Ali, Sumari, Putra, and Gandomi, Amir H.
- Abstract
The Internet of Drones (IoD) has become a hot research topic in academia, industry, and management in current years due to its wide potential applications, such as aerial photography, civilian, and military. This paper presents a comprehensive survey of IoD and its applications, deployments, and integration. We focused in this review on two main sides; IoD Applications include smart cities surveillance, cloud and fog frameworks, unmanned aerial vehicles, wireless sensor networks, networks, mobile computing, and business paradigms; integration of IoD includes privacy protection, security authentication, neural network, blockchain, and optimization based-method. A discussion highlights the hot research topics and problems to help researchers interested in this area in their future works. The keywords that have been used in this paper are Internet of Drones. [ABSTRACT FROM AUTHOR]
- Published
- 2021
- Full Text
- View/download PDF
193. Hot Chips 30.
- Author
-
Kubiatowicz, John and Rusu, Stefan
- Subjects
DYNAMIC random access memory ,AUTONOMIC computing ,VERY large scale circuit integration ,COMPUTER architecture ,COMPUTER science ,COMPUTER engineering - Published
- 2019
- Full Text
- View/download PDF
194. Call for Papers for a Special Issue of IEEE Transactions on Electron Devices on "Spintronics-Devices and Circuits".
- Subjects
HARD disks ,NANOELECTROMECHANICAL systems ,TECHNICAL textiles ,INDUSTRIAL electronics ,ELECTRONS ,COMPUTER architecture ,OPTICAL disks ,MAGNETIC sensors - Abstract
Spintronics is one of the emerging fields for the next-generation nanoscale devices offering better memory and processing capabilities with improved performance levels. It demonstrates great potential in the post-Moore era. Ever since the discovery of Giant Magneto-Resistance (GMR) effect in 1988, spintronics has shown a rapid progress. Recent advances has expanded this technology to the entire electronics industry of sensors, memories, oscillators, quantum information processors, computer architecture, brain inspired computing and various other fields. Spintronics is now one of the most researched areas and is on the verge of becoming a mainstream technology. A hard disk drive (HDD) invented by IBM in 1956, now has a global market revenue of approximately $12bn. Other emerging field of application for this technology is magnetic field sensors that showcased a market revenue of~ $19b in 2018. The magnetic memory production at major foundries such as Samsung, Globalfoundries, Western Digital and TSMC marks the adoption of spintronics technology. However, in order to meet the ever-increasing demands of the industry, innovation in terms of modeling, design, materials, processes, circuits and applications are required. This Special Issue of the IEEE Transactions on Electron Devices will feature the most recent developments and the state-of-the-art in the field of spintronic devices, circuits and new architectures for high performance. [ABSTRACT FROM AUTHOR]
- Published
- 2021
- Full Text
- View/download PDF
195. Feedforward FFT Hardware Architectures Based on Rotator Allocation.
- Author
-
Garrido, Mario, Huang, Shen-Jui, and Chen, Sau-Gee
- Subjects
FAST Fourier transforms ,DIGITAL signal processing ,ALGORITHMS ,DISCRETE Fourier transforms ,HARDWARE - Abstract
In this paper, we present new feedforward FFT hardware architectures based on rotator allocation. The rotator allocation approach consists in distributing the rotations of the FFT in such a way that the number of edges in the FFT that need rotators and the complexity of the rotators are reduced. Radix-2 and radix-2k feedforward architectures based on rotator allocation are presented in this paper. Experimental results show that the proposed architectures reduce the hardware cost significantly with respect to previous FFT architectures. [ABSTRACT FROM PUBLISHER]
- Published
- 2018
- Full Text
- View/download PDF
196. Call for Papers House Advertisement.
- Subjects
- *
COMPUTER architecture , *CONFERENCES & conventions - Abstract
Call for Papers House Advertisement [ABSTRACT FROM PUBLISHER]
- Published
- 2013
- Full Text
- View/download PDF
197. Recent developments in high-performance computing and simulation: distributed systems, architectures, algorithms, and applications.
- Author
-
Smari, Waleed W., Fiore, Sandro, and Trinitis, Carsten
- Subjects
HIGH performance computing ,SIMULATION methods & models ,COMPUTER architecture ,COMPUTER algorithms ,APPLICATION software - Published
- 2015
- Full Text
- View/download PDF
198. Editorial introduction: special issue on advances in parallel and distributed computing for neural computing.
- Author
-
Chen, Jianguo and Salah, Ahmad
- Subjects
PARALLEL programming ,DEEP learning ,HIGH performance computing ,ARTIFICIAL neural networks ,DISTRIBUTED computing ,COMPUTER architecture - Published
- 2020
- Full Text
- View/download PDF
199. Unifying Compliance Management in Adaptive Environments through Variability Descriptors (Short Paper).
- Author
-
Koetter, Falko, Kochanowski, Monika, Renner, Thomas, Fehling, Christoph, and Leymann, Frank
- Abstract
When managing IT environments and designing business processes, compliance regulations add challenges. Especially considering adaptive environments in the context of a service-oriented architecture in combination with exploiting the advantages of cloud technologies, maintaining compliance is cumbersome. Measures have to be taken on many application levels - including business processes, IT architecture, and business management. Although a lot of work has been done on various approaches covering compliance on one or more of these levels, in large companies more than one approach is likely to be employed. However, a unified approach for supporting the compliance tasks - like introduction, maintenance, and especially adaptation - on different levels of business and IT is missing. This work introduces this unifying approach, which links compliance requirements to implementing technology using variable compliance descriptors in order to comprehensively support compliance tasks. The advantage of this approach is that the impact of compliance on these different levels is tracked, thus enabling change propagation from changes in compliance requirements to infrastructure and business process reconfiguration. [ABSTRACT FROM PUBLISHER]
- Published
- 2013
- Full Text
- View/download PDF
200. Name-Centric Service Architecture for Cyber-Physical Systems (Short Paper).
- Author
-
Hellbruck, Horst, Teubler, Torsten, and Fischer, Stefan
- Abstract
The goal of Service-Oriented Architectures (SOA) is to enable easy cooperation of a large number of computers and orchestration of services that are connected via a network. However, SOA for wireless sensor networks (WSN) and cyber-physical systems (CPS) is still a challenging task. Consequently, for design and development of large CPS like WSNs connected to clouds, SOA has not yet evolved as an integral technology. One of the limiting issues is service registration and discovery. In large CPS discovery of services is tedious, mostly due to the fact that services are often semantically bound to a region or an application function while SOA forces service endpoints to be based on addresses of nodes. Also, today, SOA technologies are not used for service composition within sensor nodes and between sensor nodes, and even worse, different methods exist for service access in a WSN and in the backend. Therefore, service development differs largely in WSN and cloud. To overcome this limitation, we suggest a name-centric service architecture for cyber-physical systems. Our architecture is based on (a) using URNs instead of URLs to provide a service-centric architecture instead of service-or location-centric networking, (b) using the well-known CCNx protocol as a basis for our architecture which supports location and access transparency, and (c) employing CCN-WSN as the resource-efficient lightweight implementation for WSNs to build a name-based service bus for CPS. We evaluate the architecture by implementing an example application for facility management. [ABSTRACT FROM PUBLISHER]
- Published
- 2013
- Full Text
- View/download PDF
Discovery Service for Jio Institute Digital Library
For full access to our library's resources, please sign in.