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This paper investigates the multi-broker based network control and management paradigm for realizing scalable and cost-effective service provisioning in multi-domain software-defined optical networks. Experimental results verify the feasibility of the proposal and demonstrate ∼ 7.6× blocking reduction comparing with the conventional single-broker based solution.

Domain-Specific Languages (DSLs) provide a high-level and domain-specific abstraction to describe algorithms within a certain domain concisely. Since a DSL separates the algorithm description from the actual target implementation, it offers a high flexibility among heterogeneous hardware targets, such as CPUs and GPUs. With the recent uprise of promising High-Level Synthesis (HLS) tools, like Vivado HLS and Altera OpenCL, FPGAs are becoming another attractive target architecture. Particularly in the domain of image processing, applications often come with stringent requirements regarding performance, energy efficiency, and power, for which FPGA have been proven to be among the most suitable architectures. In this work, we present the Hipacc framework, a DSL and source-to-source compiler for image processing. We show that domain knowledge can be captured to generate tailored implementations for C-based HLS from a common high-level DSL description targeting FPGAs. Our approach includes FPGA-specific memory architectures for handling point and local operators, as well as several high-level transformations. We evaluate our approach by comparing the resulting hardware accelerators to GPU implementations, generated from exactly the same DSL source code.

Spiking Neural Network based brain-inspired computing paradigms are becoming increasingly popular tools for various cognitive tasks. The sparse event-driven processing capability enabled by such networks can be potentially appealing for implementation of low-power neural computing platforms. However, the parallel and memory-intensive computations involved in such algorithms is in complete contrast to the sequential fetch, decode, execute cycles of conventional von-Neumann processors. Recent proposals have investigated the design of spintronic “in-memory” crossbar based computing architectures driving “spin neurons” that can potentially alleviate the memory-access bottleneck of CMOS based systems and simultaneously offer the prospect of low-power inner product computations. In this article, we perform a rigorous system-level simulation study of such All-Spin Spiking Neural Networks on a benchmark suite of 6 recognition problems ranging in network complexity from 10k–7.4M synapses and 195–9.2k neurons. System level simulations indicate that the proposed spintronic architecture can potentially achieve ∼1292× energy efficiency and ∼ 235× speedup on average over the benchmark suite in comparison to an optimized CMOS implementation at 45nm technology node.

The research work explains a cost-effective, highperformance computing platform for the parallel implementation of the FDTD algorithm on PC clusters using the message-passing interface (MPI) library, which is a local area network system consisting of multiple interconnected personal computers (PCs), and is already widely employed for parallel computing.

This article discusses the 2017 ACM SIGARCH/IEEE-CS TCCA Influential ISCA Paper Award, which was given to the 2002 ISCA paper, “Drowsy Caches: Simple Techniques for Reducing Leakage Power.”

This column discusses two awards given in 2014: the International Symposium on Computer Architecture Influential Paper Award, which was given to the authors of the paper "PipeRench: A Coprocessor for Streaming Multimedia Acceleration," and the Maurice Wilkes Award, which was given to Ravi Rajwar.

Hybrid systems combine Large-Area Electronics (LAE) with high-performance technologies (e.g., silicon CMOS) [1]. With architectural concepts for hybrid systems broadening to match the range of emerging applications, this paper examines modular approaches for multi-sheet, multi-technology integration. It identifies the interfaces required as a critical backbone. For interfaces associated with various system functionalities (sensing, processing, powering), specific approaches are surveyed and analyzed, taking from insights derived from several previous experimental demonstrations of complete hybrid systems.

Latency, Area, and Power are three important metrics that a VLSI designer wants to optimize. However, often one of these may have to be optimized at the cost of another or the other two. Depending on the application scenario, choice of the metric to optimize is made. In this paper, we consider hardware implementations of a number of cryptographic primitives and present a number of optimizations. We consider three areas of cryptoengineering. They are building physical unclonable functions (PUFs), implementing encryption/decryption algorithms, and side channel proof crypto implementations. The techniques we employ range from area optimization through customized multiplexer design, fusing multiple operations into a single hardware element, folding and unrolling of iterative algorithms, creating reconfigurable implementations to achieve multiple operations with the same set of hardware elements, to techniques of obfuscation to defeat fault injection based attacks on the crypto implementation. All the proposed and existing designs are implemented with 45 nm CMOS library.

Conference of 16th International Conference on Embedded Computer Systems: Architectures, Modeling and Simulation, SAMOS 2016 ; Conference Date: 17 July 2016 Through 21 July 2016; Conference Code:126004; International audience; The Modular Microserver DataCentre (M2DC) project investigates, develops and demonstrates a modular, highly-efficient, cost-optimized server architecture composed of heterogeneous micro server computing resources, being able to be tailored to meet requirements from various application domains, including the Internet of Things. M2DC is built on three main pillars: a flexible server architecture that can be easily customised, maintained and updated; advanced management strategies and system efficiency enhancements (SEE); well-defined interfaces to surrounding software data centre ecosystem.

The review provides a survey of non-volatile, highly scalable memory devices which are based on redox phenomena controlling the resistance of nanoscale memory cells. The classification of the memory effects, the understanding of the underlying mechanisms, and a sketch of the integration efforts will be presented.

The explosion of big data applications imposes severe challenges of data processing speed and scalability on traditional computer systems. However, the performance of the von Neumann machine is greatly hindered by the increasing performance gap between CPU and memory, motivating the active research on new or alternative computing architectures. As one important instance, neuromorphic computing systems inspired by the working mechanism of human brains have gained considerable attention. In this work, we propose a heterogeneous computing system with neuromorphic computing accelerators (NCAs) that are built with emerging memristor technology. In the proposed system, NCA is designed to speed up the artificial neural network (ANN) executions in many high-performance applications by leveraging the extremely efficient mixed-signal computation capability of nanoscale memristor-based crossbar (MBC) arrays. The hierarchical MBC arrays of the NCA can be flexibly configured to different ANN topologies through the help of an analog Network-on-Chip (A-NoC). A general approach which translates the target codes within a program to the corresponding NCA instructions is also developed to facilitate the utilization of the NCA. Our simulation results show that compared to the baseline general purpose processor, the proposed heterogeneous system can achieve on average 18.2x performance speedup and 20.1x energy reduction over nine representative applications while constraining the computation accuracy degradation within an acceptable range.

This is the third special issue published in this journal with selected contributions from the VI Southern Conference on Programmable Logic (SPL, www.splconf.org). SPL is one of the first-class conferences on programmable logic around the world. Started in 2005, SPL has since 2007 the technical cosponsorship of the IEEE Circuits and Systems Society (CAS). The conference has been always organized in the south hemisphere. The selection of papers presented in this special issue is coming from the last 6th edition, held in Ipojuca, Brazil, from March 24 to 26, 2010. This issue is focused on speech and video acceleration applications. The first paper by P. Eh Kan et al., “FPGA implementation for GMM-based speaker identification” in the area of biometric-based speaker identification, describes the hardware implementation for classification of a text-independent (Gaussian mixture model) GMMbased speaker identification system. Authors show that the proposed hardware implementation allows simultaneous identification processing for a large number of voice streams in real time. In “FPGA implementation of a pipelined Gaussian calculation for HMM-based large-vocabulary speech recognition,” R. Veitch et al. present several alternatives for a Gaussian core as part of a larger speech recognition system. These cores are developed as an embedded peripheral and as a scalable, parallel hardware accelerator. Next, in “A high throughput hardware architecture for the H.264/AVC half-pixel motion estimation targeting high definition videos,” M. M. Correa et al. present a highperformance hardware implementation for the H.264/AVC half-pixel motion estimation that targets high-definition videos. This design can process very high-definition videos like QHDTV (3840 × 2048) in real time (30 frames per second). E. C. Pedrino et al. in the area of computer vision presented “A genetic programming approach to reconfigure a morphological image processing architecture.” They report the development of a reconfigurable architecture using logical, arithmetic, and morphological instructions generated automatically by a genetic programming approach. Related to cryptographic algorithms, G. Perin et al., in “Montgomery modular multiplication on reconfigurable hardware: systolic versus multiplexed implementation,” develop two Montgomery modular multiplication architectures: a systolic and a multiplexed circuit with competitive results. Finally, A. G. Silva-Filho et al. presented an advanced EDA tool in the paper “An ESL approach for energy consumption analysis of cache memories in SoC platforms” in the area of design space exploration. They propose an electronicsystem-level (ESL) approach for system modeling and cache energy consumption analysis of SoCs.

This paper presents aspects of process technology applicable to FPGAs. Overdrive of transistors for routing pass gates is an important performance and reliability factor. Random variation effects are significant for small arrays of configuration RAM, but small impact on performance. We discuss challenges for CRAM and switch replacement using novel technologies.

A dynamically reconfigurable architecture is a parallel computer architecture that supports a physical switching of communication patterns during a computation. Basically, the dynamically reconfigurable architecture consists of locally controllable switches, which enables flexible-connection patterns of the network. The bibliography attempts to classify published papers on dynamically reconfigurable architectures according to the problems that are dealt with.

This paper introduces a novel methodology to adapt the microarchitecture of a processor at run-time. The goal is to tailor the internal architecture to the requirements of an application and the data to be processed. The latter parameter is normally not known at design time. This leads to the development of more general purpose processors which are capable to handle the data to be processed in any case. With the novel approach which keeps the microarchitecture of a processor flexible, the processor can start as a general purpose device and end up with a specific parameterization, comparable with application specific processor architectures. Furthermore, the increased degree of freedom which is enabled through the approach for a novel quality of processors is described.

This paper presents a behavioral synthesis method for asynchronous circuits with bundled-data implementation. This paper extends a behavioral synthesis method for synchronous circuits so that an RTL model of bundled-data implementation is synthesized from a behavioral description specified by a restricted C language. Finally, this paper evaluates our method for several benchmarks through a tool implementation.

Scalable Video Coding provides temporal, spatial and quality scalability using layers within the encoded bitstream. This feature allows the encoded bitstream to be adapted to different devices and heterogeneous networks. This paper proposes a technique to convert an H.264/AVC bitstream in Baseline profile to a scalable stream which provides temporal scalability. Applying the presented approach, a reduction of 65% of coding complexity is achieved while maintaining the coding efficiency.

This tutorial paper surveys recent developments in parallel computer architecture, focusing on the field-programmable gate array and the graphics processor. We aim to illustrate the potential of these architectures for the type of high-speed numerical computation required in on-line optimization for model predictive control. While significant performance advantages can be gained by migrating existing control algorithms to these processor architectures, in order to realise their full potential, further research is needed at the boundary of control theory, digital electronics, and computer architecture. We survey some of the open questions in this area.

Molecular communication uses molecules (i.e., chemical signals) as an information carrier and allows biologically- and artificially-created nano- or cell-scale entities to communicate over a short distance. It is a new communication paradigm and is different from the traditional communication paradigm that uses electromagnetic waves (i.e., electronic and optical signals) as an information carrier. Key research challenges in molecular communication include design of a sender, design of a molecular propagation system, design of a receiver, design of a molecular communication interface, and mathematical modeling of molecular communication components and systems. This paper focuses on system design and experimental results of molecular communication and briefly refers to recent activities in molecular communication.

Dirty paper code (DPC) can be used in a number of communication network applications; broadcast channels, multiuser interference channels and ISI channels to name a few. We study various implementation bottlenecks and issues with implementing a DPC pre-coder based on nested trellis technique. The aim is to achieve a practical hardware realization of the precoder for wireless LAN/DSL applications. We describe the architectural development process and realization of the precoder on a Xilinx Virtex 2V8000 FPGA. To the best of our knowledge this is the first reported DPC pre-coder hardware implementation.

OpenMP has gained wide popularity as an API for parallel programming on shared memory and distributed shared memory platforms. It is also a promising candidate to exploit the emerging multicore, multithreaded processors. In addition, there is an increasing trend to combine OpenMP with MPI to take full advantage of mainstream supercomputers consisting of clustered SMPs. All of these require that attention be paid to the quality of the compiler's translation of OpenMP and the flexibility of runtime support. Many compilers and runtime libraries have an internal cost model that helps evaluate compiler transformations, guides adaptive runtime systems, and helps achieve load balancing. But existing models are not sufficient to support OpenMP, especially on new platforms. In this paper we present our experience adapting the cost models in OpenUH, a branch of Open64, to estimate the execution cycles of parallel OpenMP regions using knowledge of both software and hardware. Our OpenMP cost model reuses major components from Open64, along with extensions to consider more OpenMP details. Preliminary evaluations of the model are presented using kernel benchmarks. The challenges and possible extensions for modeling OpenMP on multicore platforms are also discussed.

This column discusses the winner of the 2012 International Symposium on Computer Architecture Influential Paper Award. It describes, from the point of view of the chair of the committee, what makes the paper influential.

Published version

International audience; Book Front Matter of AICT 313

The paper describes architectural enhancements to Xilinx FPGAs that provide better support for the creation of dynamically reconfigurable designs. These are augmented by a new design methodology that uses pre-routed IP cores for communication between static and dynamic modules and permits static designs to route through regions otherwise reserved for dynamic modules. A new CAD tool flow to automate the methodology is also presented. The new tools initially target the Virtex-II, Virtex-II Pro and Virtex-4 families and are derived from Xilinx's commercial CAD tools

The usage of mobile devices rose enormously. Their integration into complex interacting systems leads to new software architectures. This paper shows the general design considerations of service-oriented systems integrating mobile devices, together with its motivation. We identify a smaller granularity of design components - tasks for service invocation - and examine their distribution between mobile device and not mobile components of the software system.

Designing a product line architecture can be approached from scratch or by deducing it after having built a series of similar products. We hereby present a different approach where we designed a product line architecture after only one product was built. Given MCC+, a product for consistency checking of different diagrams in a UML model, we identified the variabilities it should manage in order to be useful for a variety of modeling tools, obtaining a product line MCC-SPL. We accordingly upgraded the original architecture to a product line architecture (PLA). We verified how well the proposed PLA generalizes the single product architecture using a simple yet well known product line architecture assessment method. We also validated the usefulness of the just designed PLA by porting the tool to a different modeling platform.

1 Reconfigurable Computing Group, Computer Science Department, National Institute for Astrophysics, Optics and Electronics, 72840 Puebla, PUE, Mexico 2Department of Electrical and Computer Engineering, Virginia Tech Configurable Computing Laboratory, Blacksburg, VA 24061, USA 3 Institute for Information Processing Technology (ITIV), Karlsruhe Institute of Technology (KIT), 76131 Karlsruhe, Germany