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Despite all the available commercial and open-source frameworks to ease deploying FPGAs in accelerating applications, the current schemes fail to support sharing multiple accelerators among various applications. There are three main features that an accelerator sharing scheme requires to support: exploiting dynamic parallelism of multiple accelerators for a single application, sharing accelerators among multiple applications, and providing a non-blocking congestion-free environment for applications to invoke the accelerators. In this paper, we developed a scalable fully functional hardware controller, called UltraShare, with a supporting software stack that provides a dynamic accelerator sharing scheme through an accelerators grouping mechanism. UltraShare allows software applications to fully utilize FPGA accelerators in a non-blocking congestion-free environment. Our experimental results for a simple scenario of a combination of three streaming accelerators invocation show an improvement of up to 8x in throughput of the accelerators by removing accelerators idle times.

The Life Log records computer use, details of mobile device use and sensor values collected from user's activities. Data recorded in life log is analyzed by the cloud computing and turned into useful information. Many researches to provide useful services to human beings making use of the useful information have been widely conducted. This paper surveys life log and proposes a record-preventing method and a device that is facilitated with the record-preventing function. The proposed system consists of the input component, the control component, and the output component. The input component reads data from the GPS receiver, the RFID (Radio-Frequency Identification) reader, the QR code (Quick Response Code) reader, a camera, and sensors. The control component compares the input data with the data stored in the database in order to determine whether the user is within a forbidden area. The control component stops life-logging if the user is within a forbidden area.

As SSDs are increasingly being used as high-performance storage or caches, attention is increasingly paid to the provision of SSDs with Quality-of-Service for I/O request streams of various applications in server systems. Since most SSDs are using the AHCI controller interface on a SATA bus, it is not possible to provide a differentiated service by distinguishing each I/O stream from others within the SSD. However, since a new SSD interface, the NVME controller interface on a PCI Express bus, has been proposed, it is now possible to recognize each I/O stream and schedule I/O requests within the SSD for differentiated services. This paper proposes Flash Operation Group Scheduling within NVME-based flash storage devices, and demonstrates through QEMU-based simulation that we can achieve a proportional bandwidth share for each I/O stream.

Recently, it is increasingly important to provide good real-time performance with the Android platform, since it has been used in industrial devices. The Android platform, however, does not provide a tight real-time guarantee that is required by such industrial devices as robots. Until a real-time extension of the Android platform becomes publicly available, application developers need a lightweight application-centric approach to achieve good real-time performance on the existing platform. This paper proposes an application-centric approach requiring no real-time extensions of the Android platform, which centers around multi-core partitioning and partition-aware application design. Following the proposed approach, we present an implementation study of motion control applications where the real-time tasks of the target application run on dedicated processor cores as a native Linux process while the non-real-time tasks run on other cores as an Android process. In the paper, we prove that the proposed approach is enough effective to deal with motion control applications on the existing Android platform with no real-time extensions. Our experiments show that on a quad-core Android board we can achieve such a good real-time performance as 99 % task activation jitters less than 5 µs for a motion control application with four real-time tasks and a period of 500 µs.

This paper addresses the design and implementation of an Android application for real-time precise motion control. To provide stable real-time performance, we implemented the application in two parts: Android service in the form of a daemon process, which periodically transfers a set of position commands for all motors through a real-time fieldbus, and Android UI application, which generates and delivers the set of position commands to the Android service. To support such a real-time motion control application, we use multi-core partitioning, which partitions the processor cores into a real-time partition to be used by the real-time motion control service and a non-real-time partition to be used by the Android application, and set up a shared buffer between them for communication. Our experiments show that we can obtain a motion control period of 2 ms with 99% task activation jitters less than for a configuration where each of the four threads controls two motors in a group.

Recently, to improve the user response times of Android applications, several studies have been proposed to combine the idea of Ahead-of-Time compilation into Dalvik virtual machine, which uses Just-in-Time compilation. The studies, however, require modifications of the Dalvik executables of target applications, thus are difficult to be adopted for legacy applications already deployed. This paper proposes a JITwP(JIT with Precompile) technique that precompiles hot traces at application launch time with no modification of the Dalvik executable. It improves the user response times of target applications by providing precompile hints prepared offline. Our experimental results demonstrate a 4% improvement in terms of execution time for the Web browser application.

In this paper, parallel decimal fixed-point multiplier which uses the limited range of Singed-Digit number encoding and the reduction step is proposed. The partial products are generated without carry propagation delay by encoding a multiplicand and a multiplier to the limited range of SD number. With the limited range of SD number, the proposed multiplier can improve the partial product reduction step by increasing the number of possible operands for multi-operand SD addition. In order to estimate the proposed parallel decimal multiplier, synthesis is implemented using Design Compiler with SMIC 180nm CMOS technology library. Synthesis results show that the delay of proposed parallel decimal multiplier is reduced by 4.3% and the area by 5.3%, compared to the existing SD parallel decimal multiplier. Despite of the slightly increased delay and area of partial product generation step, the total delay and area are reduced since the partial product reduction step takes the most proportion.

NAND flash memory has been widely used as a nonvolatile storage for storing data. However, it is challenging to execute program codes on NAND flash memory, since NAND flash memory only supports page-based reads, not byte-level random reads. This paper proposes an automated process to find the optimal paging strategy called RT-PLRU (Real-Time constrained combination of Pinning and LRU) that allows program codes stored in NAND flash memory to be executed satisfying real-time requirements with minimal usage of RAM. Moreover, the proposed process optimally configure the RT-PLRU in a developer-transparent way without giving any burden to the program developer. The developed technique is specifically applied to a media player program targeting a portable media player (PMP). To the best of our knowledge, this is the first effort to use NAND flash memory as a code storage for storing and executing real-time programs with minimal usage of RAM.

Application Specific Programmable Processors (ASPP) provide efficient implementation for any of m specified functionalities. Due to their flexibility and convenient performance-cost trade-offs, ASPPs are being developed by DSP, video, multimedia, and embedded lC manufacturers. In this paper, we present two low-cost approaches to graceful degradation-based permanent fault tolerance of ASPPs. ASPP fault tolerance constraints are incorporated during scheduling, allocation, and assignment phases of behavioral synthesis: Graceful degradation is supported by implementing multiple schedules of the ASPP applications, each with a different throughput constraint. In this paper, we do not consider concurrent error detection. The first ASPP fault tolerance technique minimizes the hardware resources while guaranteeing that the ASPP remains operational in the presence of all k-unit faults. On the other hand, the second fault tolerance technique maximizes the ASPP fault tolerance subject to constraints on the hardware resources. These ASPP fault tolerance techniques impose several unique tasks, such as fault-tolerant scheduling, hardware allocation, and application-to-faulty-unit assignment. We address each of them and demonstrate the effectiveness of the overall approach, the synthesis algorithms, and software implementations on a number of industrial-strength designs.

In this paper, we propose a MAC architecture for IEEE 802.11-like WLANs supporting multimedia services. The main characteristics of the proposed MAC procedure are the period restriction and DCF/SC (distributed coordination function with shortened contention-windows) instead of the PCF (point coordination function) of the IEEE 802.11 standards. We investigate the performance of the proposed MAC mechanism in terms of utilization, throughput, latency and jitter under two multimedia network environments considered by the IEEE 802.11-task group E. These environments are home and enterprise. In the simulated performance, this novel approach, which preserves the traffic classification but increases the channel utilization, thus guarantees QoS (quality of service) of multimedia traffic.

Recently, it becomes increasingly important to secure user private data in mobile devices. To protect user private data, one possible approach is to implement a secure file storage in the mobile devices based on mandatory access control (MAC), but the device manufacturers seldom implement it because of high pressure of time-to-market, frequent version upgrade of the operating system, and no unanimous agreement in the MAC standard software. In this paper, we propose an implementation study of a secure file storage, called a ghost drive, which can facilitate the implementation of MAC in the mobile devices by unburdening the manufacturers from aggressive instrumentation of the whole operating system. Since our implementation is in form of a loadable kernel module, separated from the main kernel, it can be deployed even to commercial mobile devices already in use by installing it over the air. Our experiments show that the performance of our secure storage implementation is not worse than the original unmodified implementation.

The mounting time of file system increases in embedded systems, as the capacity of flash memory keeps increasing rapidly. There is an unexpected power failure or an abnormal shutdown due to the power of mobile devices is supplied by batteries. Previous recovery schemes of the flash file system have limitation to reduce the mounting time in large flash memory and this resources constraint environment. Our goal is to reduce the reconstruction delay in flash file system. We present a state transition rate diagram of checkpoint to obtain the checkpoint interval and compute the interval of a checkpoint from the analysis of the diagram to reduce the scan time.

Mobile platforms have compute-bound applications, which will be executed on top of ARM processors in many cases. For such applications, the use of the ARM NEON technology should be considered since it can significantly increase the computing power of the underlying processor for vector operations. The ARM NEON technology is a media processing architecture based on SIMD (Single Instruction Multiple Data) that adds instructions targeted primarily for audio, video, and 3-D graphics processing. In this paper, we evaluate the ARM NEON technology in ARM Cortex-A8 processor for several open-source applications. To do this, we use the auto-vectorization feature of the ARM GCC compiler, which is implemented with the NEON technology. The evaluation criteria include program code size, execution time and power consumption, which are crucial in most embedded systems.

For advanced features of next generation vehicles, the real-time programs in automotive embedded systems are dramatically increasing. For such large volume program codes, this paper proposes a novel framework to use high-density and low-cost nonvolatile memory, i.e., NAND flash memory, as a low-cost mean of storing and executing hard real-time programs. Regarding this, one challenge is that NAND flash memory allows only 2KB page-based read operations not per-byte random access, which requires RAM as working storage for code executions. In order to minimize the expensive RAM requirements, the proposed framework optimally partitions the RAM for multiple hard real-time tasks and optimally determines the pinning/LRU combination for each RAM partition such that all task deadlines are deterministically guaranteed. The proposed framework is verified with the actual real-time programs for unmanned autonomous driving. To the best of our knowledge, this is the first work that allows us to use NAND flash memory for hard real-time program executions with the minimal usage of RAM.

NAND flash memory has been widely used as a non-volatile storage for storing data. However, it requires a large amount of SRAM for executing program codes stored in it since it only supports page-based reads, not byte-level random reads. This paper proposes a new paging mechanism called RT-PLRU (real-time constrained combination of pinning and LRU) that allows program codes stored in NAND flash memory to be executed satisfying real-time requirements with minimal usage of SRAM. Moreover, the RT-PLRU is optimally configured in a developer-transparent way without giving any burden to the program developer. The developed technique is specifically applied to a media player program targeting a PMP (portable medial player). To the best of our knowledge, this is the first effort to use NAND flash memory as a code storage for storing and executing real-time programs with minimal usage of SRAM.

The popularity of mobile and multimedia applications made real-time support a mandatory feature for embedded operating systems. However, the current situation is that the overall performance is significantly degraded due to the real-time support. This paper suggests a novel scheme to minimize the performance degradation in embedded operating systems with real-time support. Especially, we propose transparent and selective real-time interrupt services which transparently monitor the system and postpone interrupt handling that are not relevant to real-time tasks. The proposed scheme was implemented on the Linux 2.6 kernel and the experimental results show that our scheme improves the throughput by up to 86% for Hackbench benchmark while providing almost the same scheduling latency compared to the previous work.