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Background: Retrospective chart review studies may be delayed by inability to export clean clinical data from an electronic medical record (EMR) or data repository. Macros are pre-programmed procedures that can be used in Microsoft Excel to help streamline the process of cleaning clinical datasets. Objectives: To demonstrate how macros may be useful for researchers at community hospitals and smaller academic health centers that lack informatics support. Methods: Using an intrinsic function of our institution’s EMR, vital signs and lab results from 20 individual hospitalizations were exported to a spreadsheet. Two macros were developed to sort through these datasets and output them into a specified format. The speed of macro-assisted data cleaning was compared to manual transcription. Results: Time spent on data cleaning was significantly reduced when using macro-assisted sorting compared to the manual approach for both vital signs (46.5 seconds versus 12.3 minutes per record, a 94% reduction; P

This article presents a MATLAB-to-C compiler that exploits custom instructions present in state-of-the-art processor architectures and supports semi-automatic vectorization. A parameterized processor model is used to describe the target instruction set architecture to achieve user-friendly retargetability. Custom instructions are represented via specialized intrinsic functions in the generated code, which can then be used as input to any C/C++ compiler supporting the target processor. In addition, the compiler supports the generation of data parallel/vectorized code through the introduction of data packing/unpacking statements. The compiler has been used for code generation targeting ARM and x86 architectures for several benchmarks. The vectorized code generated by the compiler achieves an average speedup of 4.1× and 2.7× for packed fixed and floating point data, respectively, compared to scalarized code for ARM architecture and an average speedup of 3.1× and 1.5× for packed fixed and floating point data, respectively, for x86 architecture. Implementing data parallel instructions directly in the assembly code would have required a lot of design effort, and it would not been sustainable across evolving platform variants. Thus, the compiler can be employed to efficiently speed up critical sections of the target application. The compiler is therefore potentially employable to raise the design abstraction and reduce development time for both embedded and general-purpose applications.

Lightweight cryptography is useful to provide security and privacy in resource constraint embedded devices. Latency and memory consumption are the key elements in performance metrics for lightweight cryptography algorithm implementations. Ascon lightweight cryptography algorithm is one of the finalists in CEASAR competition. In this study, special cryptographic non-standard RISC-V instructions have been developed in order to reduce the required number of clock cycles and instruction memory for the execution of the algorithm on RV32I based processors. A profiling methodology has been developed to choose the best special instruction for achieving the highest benefit in performance. An end-to-end test environment has been formed by extending the GNU Compiler Collection and Spike RISC-V ISA Simulator for the special cryptographic instruction extensions of RISC-V processors. New intrinsic functions and instruction patterns for the new instructions have been integrated into the GCC RISC-V back end. Spike has been modified with the new instructions to run the program. The algorithm has been analysed with the proposed instructions and different optimization flags and improvement results have been shown in this study.

The technical route of machine learning compiler generally refers to the application of automatic or semi-automatic code generation in the optimization process instead of hand-optimization. This paper presents a deep learning compiler (DLCS) for target vector processor based on LLVM framework, which lowers deep learning (DL) models to an intermediate representation (IR) of two levels. The high-level IR realizes target-independent optimizations including kernel fusion, data replacement and data simplification, while the low-level IR allows the compiler to perform target-dependent optimizations, such as Eight-Slots VLIW and special intrinsic function. The proposed compiler customizes the architecture description of target vector processor to achieve a high-quality automatic code generation. We evaluate the performance comparison between DLCS and hand-optimization when deploying ResNet-18 model and MobileNet model to the target vector processor. Experimental results show that DLCS offers Multi-slot parallel performance for target vector processor and achieves speedups ranging from 1.5× to 3.0× over existing frameworks backed by hand-optimized libraries.

This paper introduces a novel domain-specific compiler, which translates visual computing programs written in dynamic languages to highly efficient code. We define "dynamic" languages as those such as Python and MATLAB, which feature dynamic typing and flexible array operations. Such language features can be useful for rapid prototyping, however, the dynamic computation model introduces significant overheads in program execution time. We introduce a compiler framework for accelerating visual computing programs, such as graphics and vision programs, written in generalpurpose dynamic languages. Our compiler allows substantial performance gains (frequently orders of magnitude) over general compilers for dynamic languages by specializing the compiler for visual computation. Specifically, our compiler takes advantage of three key properties of visual computing programs, which permit optimizations: (1) many array data structures have small, constant, or bounded size, (2) many operations on visual data are supported in hardware or are embarrassingly parallel, and (3) humans are not sensitive to small numerical errors in visual outputs due to changing floating-point precisions. Our compiler integrates program transformations that have been described previously, and improves existing transformations to handle visual programs that perform complicated array computations. In particular, we show that dependent type analysis can be used to infer sizes and guide optimizations for many small-sized array operations that arise in visual programs. Programmers who are not experts on visual computation can use our compiler to produce more efficient Python programs than if they write manually parallelized C, with fewer lines of application logic.

This paper presents the optimal implementations of single- and double-precision general matrix-matrix multiplication (GEMM) routines for the Intel Xeon Phi Processor code-named Knights Landing (KNL) and the Intel Xeon Scalable Processors based on an auto-tuning approach with the Intel AVX-512 intrinsic functions. Our auto-tuning approach precisely determines the parameters reflecting the target architectural features. Our approach significantly reduces the search space and derives optimal parameter sets including the size of submatrices, prefetch distances, loop unrolling depth, and parallelization scheme. Without a single line of assembly code, our GEMM kernels show the comparable performance results to the Intel MKL and outperform other open-source BLAS libraries.

Program comprehension is one of the most important applications in decompilation. The more abstract the decompilation result the better it is understood. Intrinsic function is introduced by a compiler to reduce the overhead of a function call and is inlined in the code where it is called. When analyzing the decompiled code with lots of inlined intrinsic functions, reverse engineers may be confused by these detailed and repeated operations and lose the goal. In this paper, we propose a method based graph isomorphism to detect intrinsic function on the CFG (Control Flow Graph) of the target function first. Then we identify the boundary of the intrinsic function, determine the parameter and return value and reduce the intrinsic function to a single function call in the disassembled program. Experimental results show that our method is more efficient at reducing intrinsic functions than the state-of-art decompilers such as Hex-Rays, REC and RD (Retargetable Decompiler).

Developing a high quality compiler tool for application-specific instruction-set processors (ASIPs) including DSP for multimedia application is challenging. The specialization in ASIPs often calls for extensions at the high-level languages to allow the designers to exploit the specialized capabilities. This in turn requires the frontend of the compiler to handle the new syntax and carry the intentions of the designers across to the compiler backend implementations. The backend implementations also require extra efforts for optimized uses of the specialize features of ASIPs. Meanwhile, because of the diversity of the application, it is necessary to make full use of the compiler to complete supports and to make up some shortages of ASIP processors, the corresponding library functions are increased to support of certain operations, such as floating point arithmetic that may not be supported in ASIPs. With the development of the embedded parallelism, the advanced ASIP compilers need the support of parallelism for future application. This paper describes the High-performance C Compiler (HCC) and its specific implementation for an industrial ASIP and its family processors. HCC is a C language compiler extended and retargeted from GCC. A compiler extension framework is proposed processing programming syntax extensions of standard ANSI C for the ASIPs. With target-specific implementation, the adding optimized arithmetic functions library and chips definition file (CDF) as well as the header files for corresponding ASIPs, HCC compiler could be enhanced for the processing capabilities of target processors. Finally, this paper describes a new compiler static allocation and scheduling scheme for loop parallelization based on the OpenMP specification to improve the load imbalance. We have conducted analysis and extensive experiments to verify the correctness and effectiveness of the HCC compiler with the presented ideas. The results show that HCC compiler has a stable performance with excellent codes quality and it has been used in market.

Short-vector SIMD and DSP instructions are popular extensions to common Isas. These extensions deliver excellent performance and compact code for some compute-intensive applications, but they require specialised compiler support. To enable the programmer to explicitly request the use of such an instruction, many C compilers provide platform-specific intrinsic functions, whose implementation is handled specially by the compiler. The use of such intrinsics, however, inevitably results in non-portable code. In this paper we develop a novel methodology for retargeting such non-portable code, which maps intrinsics from one platform to another, taking advantage of similar intrinsics on the target platform. We employ a description language to specify the signature and semantics of intrinsics and perform graph-based pattern matching and high-level code transformations to derive optimised implementations exploiting the target's intrinsics, wherever possible. We demonstrate the effectiveness of our new methodology, implemented in the FREE RIDER tool, by automatically retargeting benchmarks derived from OpenCV samples and a complex embedded application optimised to run on an Arm Cortex-M4 to an Intel Edison module with Sse4.2 instructions. We achieve a speedup of up to 3.73 over a plain C baseline, and on average 96.0% of the speedup of manually ported and optimised versions of the benchmarks.

We describe and implement an optimizing compiler transformation which turns non–tail-recursive functions into equivalent tail-recursive functions in an intermediate language of the CakeML compiler. CakeML is a strongly typed functional language based on Standard ML with call-by-value semantics and a fully verified compiler. We integrate our implementation into CakeML compiler, and provide a machine-checked proof verifying that the observational semantics of programs is preserved under the transformation. To the best of our knowledge, this is the first fully verified implementation of this transformation in any modern compiler. Moreover, our verification efforts uncover surprising drawbacks in some of the verification techniques employed in several parts of the CakeML compiler. We provide a work-around for these drawbacks, and compare it to potential alternatives.

Domain-Specific Languages (DSL's) offer language-level abstractions that General-Purpose Languages do not offer, thus speeding up the implementation of the solution of problems within a specific domain. Developers have the choice of developing a DSL by building an interpreter/compiler for it, which is a hard and time-consuming task, or embedding it in a host language, thus speeding up the development process but losing several advantages that having a dedicated compiler might bring. In this work we present a meta-compiler called Metacasanova, whose meta-language is based on operational semantics. Then, we propose a language extension with functors and modules that allows to embed the type system of a language definition inside the meta-type system of Metacasanova and improves the performance of manipulating data structures at run-time. Our results show that Metacasanova dramatically reduces the code lines required to develop a compiler, and that the running time of the Meta-program is improved by embedding the host language type system in the meta-type system with the use of functors in the meta-language.

The traditional C, C ++, Java compiler system are large and integrate a large number of libraries and frameworks, allowing developers to use conveniently, are not conducive to understand the compiler theory and technology. In this paper, aiming at the above problems, we research a simple structure of code compiler technology, developed a simple compiler system with common sense, making the reader better learn compiler theory and technology and increasing the interest of this course. Firstly, the main features and applications what Tina interpreter were discussed, and the analysis and discussion of the implementation process. The actual situation in the field of researching, proposed Tina compiler which is the design method of this solution. Secondly, from code structure and format of Tina, it analyzes the common lexical, grammatical problems. Research on the compiler technology, control structures and procedures, parsing judgment for detailed analysis. Compilation process is divided into lexical analysis, syntax analysis and code generation three processing stages,which let the Windows system as the development platform and let C language as development tools and use recursive technique and the data structure of lists and queue and stacks implementing the three modules of the specific design.

OpenFOAM is a widely used open source computational fluid dynamics (CFD) , and the performance of its application is critical for the CFD user, and many researchers try to optimize it from various perspectives. In this paper, we try to optimization OpenFOAM application from the compiler perspective, which is the simplest way to get the optimization affect. We compare two mainstream compilers: Intel compiler icc and an open source compiler, as well as a serious of optimization option flags. Through the experiment, we find that Intel compiler has a much better performance than gcc, which is up to 9.88%, and a suitable combination of the optimization option flags is important to the compile performance.

There are many domain libraries, but despite the performance benefits of compilation, domain-specific languages are comparatively rare due to the high cost of implementing an optimizing compiler. We propose commensal compilation, a new strategy for compiling embedded domain-specific languages by reusing the massive investment in modern language virtual machine platforms. Commensal compilers use the host language's front-end, use host platform APIs that enable back-end optimizations by the host platform JIT, and use an autotuner for optimization selection. The cost of implementing a commensal compiler is only the cost of implementing the domain-specific optimizations. We demonstrate the concept by implementing a commensal compiler for the stream programming language StreamJIT atop the Java platform. Our compiler achieves performance 2.8 times better than the StreamIt native code (via GCC) compiler with considerably less implementation effort., United States. Dept. of Energy. Office of Science (X-Stack Award DE-SC0008923), Intel Corporation (Science and Technology Center for Big Data), SMART3 Graduate Fellowship

Along with quad-core PC coming into the market and invention of 80-core processor in the laboratory, Software development will go through a foundational innovation due to multicore technology. The technique of parallel programming on multi-core computers is explored in this thesis. First, the OpenMP standard which is an application programming interface (API) on parallel programming model of shared-memory is introduced and an overview of a set of compiler directives and a library of support functions are given. The OpenMP programs requires an OpenMP-compatible compiler and thread-safe libraries，therefore, both Intel C++ compiler 9.1 and Microsoft Visual Studio 2005 are perfect choices. Then, two-dimensional discrete fast Fourier transform (FFT) is studied by focusing on parallel program design，realization and optimization technology. Finally，the thesis predicts that high performance parallel computing software component library must be a perfect exploitation field in the further future.

This paper implements Tiger compiler on Hacs language. This compiler is likely to perform many or all of the following operations: lexical analysis, preprocessing, parsing, semantic analysis, and code optimization, target code generation. These are discussed in this paper in detail. As a new design language compiler, Hacs has the prominent advantages of high portability, maintainability and so on .It is easy to achieve.

The dataflow programming paradigm shows an important way to improve programming productivity for streaming systems. In this paper we propose COStream, a programming language based on synchronous data flow execution model for data-driven application. We also propose a compiler framework for COStream on general-purpose multi-core architectures. It features an inter-thread software pipelining scheduler to exploit the parallelism among the cores. We implemented the COStream compiler framework on x86 multi-core architecture and performed experiments to evaluate the system.

The GCC is an auto-vectorization compiler across iterations of loops to parallelism data. Turning GCC compiler optimizations flags for auto-vectorization is a way to improve the performance ability, which is a popular approach to speed up program performance. However, there are many options in GCC compiler and selecting the best combination of these options to improve program performance through vectorization is non-trivial ( as the search space is very large ).In this work we focus on the selection of compiler transformations to auto-vectorize loops with conditional statements. The selection of compiler transformations is based on the correlation between program features, speed-up, and the analysis of the code generated and a small number of passes of iterative compilation. Our preliminary experimental results show that proposed technique attains performance improvements the best ~ 6x using loops in the TSVC benchmark suite on the state-of-the-art Intel Core i3 processor.

Expressing algorithms using immutable arrays greatly simplifies the challenges of automatic SIMD vectorization, since several important classes of dependency violations cannot occur. The Haskell programming language provides libraries for programming with immutable arrays, and compiler support for optimizing them to eliminate the overhead of intermediate temporary arrays. We describe an implementation of automatic SIMD vectorization in a Haskell compiler which gives substantial vector speedups for a range of programs written in a natural programming style. We compare performance with that of programs compiled by the Glasgow Haskell Compiler.

This paper studies the application programming interface in configuration software. Based on comprehensively considering softwares application, a mini-message bus configuration languageMMBCL language is designed by using C language, whose compiler and development environment are fulfilled. The designing, syntax analysis, semantic analysis of MMBCL are deeply discussed. This configuration language is simple, similar to C language, easy to write, consistent with industrial control standard. And it has successfully applied to the industrial project and proves the efficiencies of the configuration language and the compiler.

Short-vector S imd and D sp instructions are popular extensions to common I sa s. These extensions deliver excellent performance and compact code for some compute-intensive applications, but they require specialized compiler support. To enable the programmer to explicitly request the use of such an instruction, many C compilers provide platform-specific intrinsic functions, whose implementation is handled specially by the compiler. The use of such intrinsics, however, inevitably results in nonportable code. In this article, we develop a novel methodology for retargeting such nonportable code, which maps intrinsics from one platform to another, taking advantage of similar intrinsics on the target platform. We employ a description language to specify the signature and semantics of intrinsics and perform graph-based pattern matching and high-level code transformations to derive optimized implementations exploiting the target’s intrinsics, wherever possible. We demonstrate the effectiveness of our new methodology, implemented in the F ree R ider tool, by automatically retargeting benchmarks derived from O pen CV samples and a complex embedded application optimized to run on an A rm C ortex -M4 to an I ntel E dison module with S se 4.2 instructions (and vice versa). We achieve a speedup of up to 3.73 over a plain C baseline, and on average 96.0% of the speedup of manually ported and optimized versions of the benchmarks.

Recent trends in processor design accommodate wide vector extensions. SIMD vectorization is more important than before to exploit the potential performance of the target architecture. The latest OpenMP specification provides new directives which help compilers produce better code for SIMD auto-vectorization. However, it is hard to optimize the SIMD code performance in OpenMP since the target SIMD code generation mostly relies on the compiler implementation. In this paper, we propose a new directive that specifies user-defined SIMD variants of functions used in SIMD loops. The compiler can then use the user-defined SIMD variants when it encounters OpenMP loops instead of auto-vectorized SIMD variants. The user can optimize the SIMD performance by implementing highly-optimized SIMD code with intrinsic functions. The performance evaluation using a image composition kernel shows that the user can optimize SIMD code generation in an explicit way by using our approach. The user-defined function reduces the number of instructions by 70% compared with the auto-vectorized code generated from the serial code.

Considering the fact that Marc is based on the Fortran programming language, not only is the basic knowledge of the language is indispensable, but becoming familiar with advanced features will definitely improve the structure of the code. In this chapter, a comprehensive review of the advanced capabilities of the Fortran language will be presented.

Modern compilers can work on many platforms and implement a lot of optimizations, which are not always tuned well for every target platform. In the paper we present the Tool for Automatic Compiler Tuning (TACT), which helps to identify such underperforming compiler optimizations. Using GCC for ARM, we show how this tool can be used to improve performance of several popular applications, and how the results can be further analyzed to find places for improvement in the GCC compiler itself.

Presented is the Quiet Direct Simulation (QDS) applied to parallel computation using a hybrid OpenMP/AVX parallelization paradigm. Due to the high locality of the QDS scheme, the method has been successfully applied to parallel computation using Graphics Processing Units (GPU) – we show here that the same principles which allow high performance on GPU devices also permit high performance when using Advanced Vector eXtensions (AVX). Furthermore, since modern CPU's employ a large number of cores, we can further extend the performance by using AVX on each available CPU core using shared memory (OpenMP) parallelization. We present a simple direction- split higher order extension to the QDS method, and then apply it to AVX through the use of intrinsic functions in the flux computation and state computation modules. High performance is obtained by ensuring that all flux computations are performed using only AVX intrinsic functions – no computations are performed in serial. Through this approach, a single workstation with 2x Xeon CPU's (16 physical cores) allows a performance increase of over 177 times that of a single core alone. We also demonstrate that built-in optimization does not fully exploit AVX parallelization through the examination of assembly code.

The following work describes a project development of the C compiler for computing systems with programmable architectures. The compiler has been implemented on the base of OPS (Optimizing Parallelizing System, http://ops.rsu.ru) and a converter of C language into VHDL (C2HDL). An example of the compiler use has been presented in the article.

We have developed and mechanically verified a new compiler backend for CakeML. Our new compiler features a sequence of intermediate languages that allows it to incrementally compile away high-level features and enables verification at the right levels of semantic detail. In this way, it resembles mainstream (unverified) compilers for strict functional languages. The compiler supports efficient curried multi-argument functions, configurable data representations, exceptions that unwind the call stack, register allocation, and more. The compiler targets several architectures: x86-64, ARMv6, ARMv8, MIPS-64, and RISC-V. In this paper, we present the overall structure of the compiler, including its 12 intermediate languages, and explain how everything fits together. We focus particularly on the interaction between the verification of the register allocator and the garbage collector, and memory representations. The entire development has been carried out within the HOL4 theorem prover.

This paper analyzes structural features of the prolog compiler on the basis of its executive mechanism. The main focus of the research targets the functional characteristics and the working mechanism of the compiler through the analysis of prolog language organizing and translating procedure in conjunction with the logic-reasoning attribute of the language. The paper illustrates structure of three important modules and demonstrates their corresponding realization method. The research of lexical compiler will lay a foundation for future works of upgrading and developing Prolog compiler.

The VLIW architecture can be exploited to greatly enhance instruction level parallelism, thus it can provide computation power and energy efficiency advantages, which satisfies the requirements of future sensor-based systems. However, as VLIW codes are mainly compiled statically, the performance of a VLIW processor is dominated by the behavior of its compiler. In this paper, we present an advanced compiler designed for a VLIW DSP named Magnolia, which will be used in sensor-based systems. This compiler is based on the Open64 compiler. We have implemented several advanced optimization techniques in the compiler, and fulfilled the O3 level optimization. Benchmarks from the DSPstone test suite are used to verify the compiler. Results show that the code generated by our compiler can make the performance of Magnolia match that of the current state-of-the-art DSP processors.

Upon binding to a receptor, agonists and antagonists can induce distinct biological functions and thus lead to significantly different pharmacological responses. Thus, in silico prediction or in vitro characterization of ligand agonistic or antagonistic functionalities is an important step toward identifying specific pharmacological therapeutics. In this study, we investigated the molecular properties of agonists and antagonists of human 5-hydroxytryptamine receptor subtype 1A (5-HT 1A ). Subsequently, intrinsic functions of these ligands (agonists/antagonists) were modeled by support vector machine (SVM), using five 2D molecular fingerprints and the 3D Topomer distance. Five kernel functions, including linear, polynomial, RBF, Tanimoto and a novel Topomer kernel based on Topomer 3D similarity were used to develop linear and nonlinear classifiers. These classifiers were validated through cross-validation, yielding a classification accuracy ranging from 80.4% to 92.3%. The performance of different kernels and fingerprints was analyzed and discussed. Linear and nonlinear models were further interpreted through the illustration of underlying classification mechanism. The computation protocol has been automated and demonstrated through our online service. This study expands the scope and applicability of similarity-based methods in cheminformatics, which are typically used for the identification of active molecules against a target protein. Our findings provide a good starting point for further systematic classifications of other GPCR ligands and for the data mining of large chemical libraries. Copyright © 2012 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim.

The hardware and programming of lane boundary identification system, which based on the hardware platform of DM642, designed. The system complete the functions of acquiring image data, optimizing acquired data by ant algorithm, comparing value by the objective function, exporting image of lane boundary and so on. For the sake of improving the real time capability further, optimize code by way of methods, which include the optimization of compiler, intrinsic function, packaging data, using pipeline technique, and assembly code, giving specific optimization methods and real time capability of algorithm affected by each process. As a result the identification time of system reduced from 101.75 ms to 20.55ms, improved the system of real time capability effectively, laying a good foundation for industry.

The past decade has produced numerous CPU architectural innovations. These have included multiple cores per CPU, multiple simultaneous threads per core, and, especially with GPUs, highly complex memory hierarchies. As a result, performance porta-bility has become a major challenge to programmers. We identify the SIMD engines in modern CPU and GPU cores as the key to obtaining high performance for scientific application codes. This common element of all present computing devices makes performance portability possible. However, we find that achieving this performance requires us to express the code in terms of intrinsic functions for the SIMD engine instructions, and these functions are different for each device. To assist the programmer in creating the necessary code expressions for each vendor's compilers, we have built an automated code translator that takes as input a single Fortran source code, written in a special style and annotated with directives, and creates output code for each device and compiler combination. The manual translations for GPU permit us here to evaluate the performance that our code transformations deliver on these devices. We present a performance study using our single-fluid PPM gas dynamics code and covering the latest multi-core processors and the Nvidia GPU.

Reconfigurable computing using a field-programmable gate-array (FPGA) device has become a promising solution in system design because of its power efficiency and design flexibility. To bring the benefit of FPGA to many application programmers, there has been intensive research about automatic translation from high-level programming languages (HLL) such as C and C++ into hardware. However, the large gap of syntaxes and semantics between hardware and software programming makes the translation challenging. In this paper, we introduce a new approach for the translation by using the widely used GCC compiler. By simply adding a hardware description language (HDL) backend to the existing state-of-the-art compiler, we could minimize an effort to implement the translator while supporting full features of HLL in the HLL-to-HDL translation and providing high performance. Our translator, called GCC2Verilog, was implemented as the GCC’s cross compiler targeting at FPGAs instead of microprocessor architectures. Our experiment shows that we could achieve a speedup of up to 34 times and 17 times on average with 4-port memory over PICO microprocessor execution in selected EEMBC benchmarks. Keywords: HLL-to-HDL translator, GCC2Verilog, FPGA, compiler.

This paper proposes a method of software development tool generation suitable for instruction set extension of existing embedded processors. The key idea in the proposed method is to enhance a base processor's toolchain by adding plugins, which are software components that handle additional instructions and registers. The proposed method can generate a compiler, assembler, disassembler, and instruction set simulator. Generated compilers with the plugins provide intrinsic functions that are translated directly into the new instructions. To demonstrate that the proposed method works effectively, this paper presents an experimental result of the proposed method in the study of adding SIMD instructions to the embedded microprocessor V850. In the experiment, by using intrinsic functions, the compiler generated good code with only 7% increase in the number of instructions against the hand-optimized assembly codes.

This paper develops a standard conforming generic linked list in Fortran 95 which is capable of storing data of any type. The list is implemented using the transfer intrinsic function, and although the interface is generic, it remains relatively simple and minimizes the potential for error. Although linked lists are the focus of this paper, the generic programming techniques used are very general and broadly-applicable to other data structures and procedures implemented in Fortran 95 that need to be used with data of an unknown type.

International audience; This paper reports on the development and formal verification (proof of semantic preservation) of CompCert, a compiler from Clight (a large subset of the C programming language) to PowerPC assembly code, using the Coq proof assistant both for programming the compiler and for proving its correctness. Such a verified compiler is useful in the context of critical software and its formal verification: the verification of the compiler guarantees that the safety properties proved on the source code hold for the executable compiled code as well.

In recent years, the GPU (graphics processing unit) has evolved into an extremely powerful and flexible processor, with it now representing an attractive platform for general-purpose computation. Moreover, changes to the design and programmability of GPUs provide the opportunity to perform general-purpose computation on a GPU (GPGPU). Even though many programming languages, software tools, and libraries have been proposed to facilitate GPGPU programming, the unusual and specific programming model of the GPU remains a significant barrier to writing GPGPU programs. In this paper, we introduce a novel compiler-based approach for GPGPU programming. Compiler directives are used to label code fragments that are to be executed on the GPU. Our GPGPU compiler, Guru, converts the labeled code fragments into ISO-compliant C code that contains appropriate OpenGL and Cg APIs. A native C compiler can then be used to compile it into the executable code for GPU. Our compiler is implemented based on the Open64 compiler infrastructure. Preliminary experimental results from selected benchmarks show that our compiler produces significant performance improvements for programs that exhibit a high degree of data parallelism.

International audience; SIGNAL belongs to the synchronous languages family which are widely used in the design of safety-critical real-time systems such as avionics, space systems, and nuclear power plants. This paper reports a compiler prototype for SIGNAL. Compared with the existing SIGNAL compiler, we propose a new intermediate representation (named S-CGA, a variant of clocked guarded actions), to integrate more synchronous programs into our compiler prototype in the future. The front-end of the compiler, i.e., the translation from SIGNAL to S-CGA, is presented. As well, the proof of semantics preservation is mechanized in the theorem prover Coq. Moreover, we present the back-end of the compiler, including sequential code generation and multithreaded code generation with time-predictable properties. With the rising importance of multi-core processors in safety-critical embedded systems or cyber-physical systems (CPS), there is a growing need for model-driven generation of multithreaded code and thus mapping on multi-core. We propose a time-predictable multi-core architecture model in architecture analysis and design language (AADL), and map the multi-threaded code to this model.

© 2016 EDAA. This paper discusses a MATLAB to C compiler exploiting custom instructions such as instructions for SIMD processing and instructions for complex arithmetic present in Application Specific Instruction Set Processors (ASIPs). The compiler generates ANSI C code in which the processor's special instructions are represented via specialized intrinsic functions. By doing this the generated code can be used as input to any C/C++ compiler. Thus the proposed compiler allows the description of the specialized instruction set of the target processor in a parameterized way allowing the support of any processor. The proposed compiler has been used for the generation of application code for an ASIP targeting DSP applications. The code generated by the proposed compiler achieves a speed up between 2x-30x on the targeted ASIP for six DSP benchmarks compared to the code generated by Mathworks MATLAB to C compiler. Thus the proposed compiler can be employed to reduce the development time/effort/cost and time to market by raising the abstraction of application design in an embedded systems / system-on-chip development context while still improving implementation efficiency. ispartof: pages:1453-1456 ispartof: PROCEEDINGS OF THE 2016 DESIGN, AUTOMATION & TEST IN EUROPE CONFERENCE & EXHIBITION (DATE) vol:22 issue:2 pages:1453-1456 ispartof: Design, Automation and Test in Europe Conference and Exhibition (DATE) location:GERMANY, Dresden date:14 Mar - 18 Mar 2016 status: published

In traditional compiler construction courses, each compiler phase is studied in detail before moving on to the next one. This not only places a great distance between theory and practice but also makes the students lose the big picture of the subject. We have been employing a different course format in which the subject is incrementally introduced through ten compilers of increasingly complexity. The first compiler is in fact just a syntax analyzer of a very simple language. The last one is a complete compiler of a Pascal-like language. Students of this course learn how to build compilers faster than the usual.

We present a technique for implementing visual language compilers through standard compiler generation platforms. The technique exploits eXtended Positional Grammars (XPGs, for short) for modeling the visual languages in a natural way, and uses a set of mapping rules to translate an XPG specification into a translation schema. This lets us generate visual language parsers through standard compiler-compiler techniques and tools like YACC. The generated parser accepts exactly the same set of visual sentences derivable through the application of XPG productions. The technique represents an important achievement, since it enables us to perform visual language compiler construction through standard compiler-compilers rather than specific compiler generation tools. This makes our approach particularly appealing, since compiler-compilers are widely used and rely on a well-founded theory. Moreover, the approach provides the basis for the unification of traditional textual language technologies and visual language compiler technologies.

SUMMARY OpenMP has gained wide popularity as an API for parallel programming on shared memory and distributed shared memory platforms. Despite its broad availability, there remains a need for a portable, robust, open source, optimizing OpenMP compiler for C/C++/Fortran 90, especially for teaching and research, for example into its use on new target architectures, such as SMPs with chip multi-threading, as well as learning how to translate for clusters of SMPs. In this paper, we present our efforts to design and implement such an OpenMP compiler on top of Open64, an open source compiler framework, by extending its existing analysis and optimization and adopting a source-to-source translator approach where a native back end is not available. The compilation strategy we have adopted and the corresponding runtime support are described. The OpenMP validation suite is used to determine the correctness of the translation. The compiler’s behavior is evaluated using benchmark tests from the EPCC microbenchmarks and the NAS parallel benchmark. Copyright c � 2007 John Wiley & Sons, Ltd.

Determining nearly optimal optimization options and selecting the right values for compiler parameter set is a combinatorial problem. In order to obtain the maximal performance, sophisticated tuning strategies were employed by many researchers. Enormous tuning times are the main hindrance for the application of these strategies in production compilers. Also the existing compiler optimization frameworks do not completely capture the requirements of modern day systems and their performance objectives. In order to mitigate the problem of enormous tuning times and also to capture the requirements of the modern day systems, we are proposing a novel scheme for Compiler Optimization Framework, called Compiler Optimization Adaption Scheme. As part of this scheme, we propose the Objective-specific Tuned Libraries, which will be used to link with the applications as per the desired performance objective. Details of the experimentation supporting our ideas behind the scheme including Objective-specific Tuned Libraries are also presented.

This paper presents a new approach to efficiently search for suitable compiler pass sequences, a challenge known as phase ordering. Our approach relies on information about the relative positions of compiler passes in compiler pass sequences previously generated for a set of functions when compiling for a specific processor. We enhanced two iterative compiler pass exploration schemes, one relying on simple sequential compiler pass insertion and other implementing an auto-tuned simulated annealing process, with a data structure that holds information about the relative positions of compiler sequences; in order to reduce the set of compiler passes considered for insertion in a given position of a given candidate compiler pass sequence to include only the passes that have a higher probability of performing well on that relative position in the compiler sequence, speeding up the exploration time as a result. We tested our approach with two different compilers and two different targets; the ReflectC and the LLVM compilers, targeting a MicroBlaze processor and a LEON3 processor, respectively. The experimental results show that we can considerably reduce the number of algorithm iterations by a factor of up to more than an order of magnitude when targeting the MicroBlaze or the LEON3, while finding compiler sequences that result in binaries that when executed on the target processor/simulator are able to outperform (i.e. use less CPU cycles) all the standard optimization levels (i.e., we compare against the most performing optimization level flag on each kernel, e.g. -O1, -O2 or -O3 in the case of LLVM) by a geometric mean performance improvement of 1.23x and 1.20x when targeting the MicroBlaze processor, and 1.94x and 2.65x when targetting the LEON3 processor; for each of the two exploration algorithms and two kernel sets considered.

This grant supported the ZettaBricks and OpenTuner projects. ZettaBricks is a new implicitly parallel language and compiler where defining multiple implementations of multiple algorithms to solve a problem is the natural way of programming. ZettaBricks makes algorithmic choice a first class construct of the language. Choices are provided in a way that also allows our compiler to tune at a finer granularity. The ZettaBricks compiler autotunes programs by making both fine-grained as well as algorithmic choices. Choices also include different automatic parallelization techniques, data distributions, algorithmic parameters, transformations, and blocking. Additionally, ZettaBricks introduces novel techniques to autotune algorithms for different convergence criteria. When choosing between various direct and iterative methods, the ZettaBricks compiler is able to tune a program in such a way that delivers near-optimal efficiency for any desired level of accuracy. The compiler has the flexibility of utilizing different convergence criteria for the various components within a single algorithm, providing the user with accuracy choice alongside algorithmic choice. OpenTuner is a generalization of the experience gained in building an autotuner for ZettaBricks. OpenTuner is a new open source framework for building domain-specific multi-objective program autotuners. OpenTuner supports fully-customizable configuration representations, an extensible technique representation to allow for domain-specificmore » techniques, and an easy to use interface for communicating with the program to be autotuned. A key capability inside OpenTuner is the use of ensembles of disparate search techniques simultaneously; techniques that perform well will dynamically be allocated a larger proportion of tests.« less

The performance of Java has been tremendously improved by the advance of Just-in-Time (JIT) compilation technologies. However, debugging such a dynamic compiler is much harder than a static compiler. Recompiling the problematic method to produce a diagnostic output does not necessarily work as expected, because the compilation of a method depends on runtime information at the time of compilation.In this paper, we propose a new approach, called replay JIT compilation , which can reproduce the same compilation remotely by using two compilers, the state-saving compiler and the replaying compiler . The state-saving compiler is used in a normal run, and, while compiling a method, records into a log all of the input for the compiler. The replaying compiler is then used in a debugging run with the system dump, to recompile a method with the options for diagnostic output. We reduced the overhead to save the input by using the system dump and by categorizing the input based on how its value changes. In our experiment, the increase of the compilation time for saving the input was only 1%, and the size of the additional memory needed for saving the input was only 10% of the compiler-generated code.

Optional parameters are a feature of Fortran90. The objective of this feature is to allow the F90 programmer to declare a subroutine using a number of arguments and specify a subset of these parameters as optional , which in turn, allows the programmer to omit any of these optional parameters during invocation of the subroutine. The body of such a subroutine uses an F90 intrinsic function called present() , to test whether an optional parameter has meaningful values at run-time. The optional parameter can be written/read if and only if present() returns a true value. In this work, we describe a mechanism by which such subroutines which use optional parameters can be efficiently optimized using function cloning or specialization. Function Cloning is a well-known optimization technique that creates multiple copies of a function f() , in order to exploit better optimization opportunities. We will show how cloning/specialization can be utilized such that all calls to present() can be totally eliminated in the body of such subroutines. Cloning will also result in optimization opportunities not exploitable in the original source.

ADF95 is a tool to automatically calculate numerical first derivatives for any mathematical expression as a function of user defined independent variables. Accuracy of derivatives is achieved within machine precision. ADF95 may be applied to any FORTRAN 77/90/95 conforming code and requires minimal changes by the user. It provides a new derived data type that holds the value and derivatives and applies forward differencing by overloading all FORTRAN operators and intrinsic functions. An efficient indexing technique leads to a reduced memory usage and a substantially increased performance gain over other available tools with operator overloading. This gain is especially pronounced for sparse systems with large number of independent variables. A wide class of numerical simulations, e.g., those employing implicit solvers, can profit from ADF95., Comment: 24 pages, 2 figures, 4 tables, accepted in Computer Physics Communications