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Dedicated infrastructures are commonly used for urgent computations. However, using dedicated resources is not always affordable due to budget constraints. As a result, utilizing shared infrastructures becomes an alternative solution for urgent computations. Since the infrastructures are meant to serve many users, the urgent jobs may arrive when regular jobs are using the necessary resources. In such a case, it is necessary to preempt the regular jobs so that urgent jobs can be executed immediately. Most conventional methods for job scheduling have focused on reducing the response times and waiting times of all jobs. However, these methods can delay urgent jobs and hinder them from being completed within a stipulated deadline. Furthermore, in heterogeneous systems with coprocessors, preemption becomes more difficult because coprocessors rely on several system software functionalities provided by the host processor. In this paper, we propose a parallel job scheduling method to effectively use shared heterogeneous systems for urgent computations. Our method employs an in-memory process swapping mechanism to preempt jobs running on the coprocessor devices. The results of our simulations show that our method can achieve a significant reduction in the response time and slowdown of regular jobs without substantial delays of urgent jobs.

This paper presents an extension of Kokkos for modern vector processors, such as Vector Engines of SX-Aurora TSUBASA (VEs). Kokkos is a C++ library that provides polymorphic memory access patterns, and widely used for keeping high performance portability of applications. Although Kokkos does not officially support VEs as of July 2020, VEs can execute standard C++ programs, and the original Kokkos can indeed be compiled for VEs. However, the memory access pattern provided by Kokkos for standard processors is not necessarily suited for VEs. For example, it is known that memory access conflicts could drastically degrade the sustained memory bandwidth on VEs, even though, for memory access conflicts, standard processors assumed in Kokkos, i.e., x86 processors, are less performance-sensitive than VEs. Therefore, we propose an extended Kokkos implementation for VEs, which can provide memory access patterns suited for VEs. Specifically, we mainly focus on avoiding memory access conflicts on VEs. This paper introduces a mechanism to automatically avoid memory access conflicts, and explains its implementation. We evaluate our proposal using some benchmark codes, and the results demonstrate that our proposal can successfully exploit the high memory bandwidth of VEs.

Although there are various ways of implementing sparse matrix vector multiplication (SpMV), there is no established way of predicting the best implementation for individual sparse matrices, and thus an SpMV implementation has empirically been selected for each matrix. Cui et al. have proposed a machine learning approach to the prediction. However, their approach focuses only on predicting the best implementation for each matrix, and does not consider the performance differences among candidate implementations. If the performance difference between the best and non-best implementations for a matrix is large, the performance loss by the misprediction is also large. Thus, a machine learning model needs to be trained to preferentially avoid misprediction of such a matrix to achieve a higher expected performance. Therefore, this paper presents a machine learning approach that considers the performance differences at the best SpMV implementation selection problem and quantitatively discusses the performance improvement by the approach. The evaluation results clearly demonstrate that the proposed approach can prevent a machine learning model from selecting significantly low-performance implementations, and thereby improve the expected performance in comparison with the previous approach.

The emergence of various high-performance computing (HPC) systems compels users to write a code considering the characteristic of each HPC system. To describe the system-dependent information without drastic code modifications, the directive sets such as the OpenMP directive set and the OpenACC directive set are proofed to be useful. However, the code becomes complex to achieve high performance on various HPC systems because different directive sets are required for various HPC systems. Thus, the code-maintainability and readability are degraded. This paper proposes a directive generation approach that generates various kinds of directive sets using user-defined rules. Instead of using several kinds of directive sets, users only have to write special placeholders that are utilized to specify a unique code pattern where several directives are inserted. Then, the special placeholders trigger the generation of appropriate directives for each system using a user-defined rule with a code transformation framework Xevolver . Because only special placeholders are inserted in the code, the proposed approach can keep the code-maintainability and readability. From the performance evaluations of directive-based implementations on various HPC systems, it is shown that the best implementation is different among the HPC systems. Then, through the demonstration of transformation into multiple kinds of implementations, the proposed approach can successfully generate directives from a smaller number of special placeholders. Therefore, it is clarified that the proposed directive generation approach is effective to keep the maintainability of a code to be executed on various HPC systems.

This paper presents an OpenCL-like offload programming framework for NEC SX-Aurora TSUBASA (SXAurora). Unlike traditional vector systems, one node of an SXAurora system consists of a host processor and some vector processors on PCI-Express cards, which are called a vector host and vector engines, respectively. Since the standard OpenCL execution model does not naturally fit in the vector engine, this paper discusses how to adapt the OpenCL specification to SXAurora while considering the trade off between performance and code portability. Performance evaluation results clearly demonstrate that, with a moderate programming effort, the proposed framework can express the collaboration between a vector host and a vector engine so as to make a good use of both of the two different processors. By delegating the right task to the right processor, an OpenCL-like program can fully exploit the performance of SX-Aurora.

This paper presents an OpenCL-like offload programming framework for NEC SX-Aurora TSUBASA (SX-Aurora) and also discusses the benefit of employing metaprogramming to describe architecture-specific parts of the programs. Unlike traditional vector systems, one node of an SX-Aurora system consists of a host processor and some vector processors on PCI-Express cards, which are called a vector host and vector engines, respectively. Since the standard OpenCL execution model does not naturally fit in the vector engine, this paper discusses how to adapt the OpenCL specification to SX-Aurora while considering the trade off between performance and code portability. This paper employs OpenCL to minimize non-portable parts of an application code for offload programming, and then metaprogramming to describe the non-portable parts. Performance evaluation results clearly demonstrate that, with a moderate programming effort, the proposed framework can express the collaboration between a vector host and a vector engine so as to make a good use of both of the two different processors. By delegating the right task to the right processor, an OpenCL-like program can fully exploit the performance of SX-Aurora. Moreover, metaprogramming can express vectorization-aware performance optimization to enhance the performance portability across different architectures including SX-Aurora.

Most machine learning models use hyperparameters empirically defined in advance of their training processes in a time-consuming and try-and-error fashion. Hence, there is a strong demand for systematically finding an appropriate hyperparameter configuration in a practical time. Recent works have been interested in Bayesian Optimization to tune the hyperparameters with a less number of trials, using a Gaussian Process to determine the next hyperparameter configuration being sampled for evaluation. Most of the works use some criteria including the probability of improving (GP-PI), the expected improvement (GP-EI), and the upper confidence bounds (GP-UCB), without consideration of the execution time of each trial. In this paper, we focus on minimizing the total execution time to find an appropriate configuration. Specifically, we propose to take the execution time of each trial into account. We demonstrate the feasibility of the proposed approach and show that our proposal can find an optimal or suboptimal hyperparameter configuration faster than other Bayesian optimization-based approaches in terms of execution time.

Since it is difficult to explicitly express the underlying relationship between a code and appropriate optimizations for it, this paper discusses a possibility of using machine learning to predict appropriate optimizations for a given code. In this paper, selection of appropriate compiler options is taken as an example of the prediction, because it can be seen as selection of code optimizations; use of different compiler options results in enabling different compiler optimizations. One severe problem is that it is difficult to collect a sufficient number of data for a machine learning model to well understand the underlying relationships among codes and their appropriate optimizations. Therefore, in addition to conventional features of a code, such as profiling data and parameterized code features, we directly use a code structure itself to retrieve more information from a limited number of codes. The evaluation results suggest that use of code structural features can potentially improve the prediction accuracy if the training dataset contains data of similar code structures.

A code smell is a code pattern that might indicate a code or design problem, which makes the application code hard to evolve and maintain. Automatic detection of code smells has been studied to help users find which parts of their application codes should be refactored. However, code smells have not been defined in a formal manner. Moreover, existing detection tools are designed mainly for object-oriented applications, but rarely provided for high performance computing (HPC) applications. HPC applications are usually optimized for a particular platform to achieve a high performance, and hence have special code smells called platform-specific code smells (PSCSs). The purpose of this work is to develop a code smell alert system to help users find PSCSs of HPC applications to improve the performance portability across different platforms. This paper presents a PSCS alert system that is based on an abstract syntax tree (AST) and XML. Code patterns of PSCSs are defined in a formal way using the AST information represented in XML. XML Path Language (XPath) is used to describe those patterns. A database is built to store the transformation recipes written in XSLT files for eliminating detected PSCSs. The recall and precision evaluation results obtained by using real applications show that the proposed system can detect potential PSCSs accurately. The evaluation on performance portability of real applications demonstrates that eliminating PSCSs leads to significant performance changes and therefore the code portions with detected PSCSs have to be refactored to improve the performance portability across multiple platforms.Â

The rapid evolution of HPC systems brings us a high computational capability. However, it is getting harder to exploit the potential of an HPC system due to the increases in system complexity. This fact forces computational scientists to create complicated programming, which causes low productivity and maintainability. To overcome this situation, we are aggregating various optimization patterns and building a knowhow database of system-aware code optimizations called an HPC refactoring catalog. This paper discusses the design and implementation of an HPC refactoring catalog and shows a case study to demonstrate the practicality of the catalog.

The cost of maintaining an application code would significantly increase if the application code is branched into multiple versions, each of which is optimized for a different architecture. In this work, default and vector versions of a realworld application code are refactored to be a single version, and the differences between the versions are expressed as userdefined code transformations. As a result, application developers can maintain only the single version, and transform it to its vector version just before the compilation. Although code optimizations for a vector processor are sometimes different from those for other processors, application developers can enjoy the performance of the vector processor without increasing the code complexity. Evaluation results demonstrate that vectorizationaware loop optimization for a vector processor can be expressed as user-defined code transformation rules, and thereby significantly improve the performance of a vector processor without major code modifications.

Coordinated checkpointing is a widely-used checkpoint/restart (CPR) technique for fault-tolerance in large-scale HPC systems. However, this CPR technique will involve massive amounts of I/O concentration, resulting in considerably high checkpoint overhead and high energy consumption. This paper focuses on multi-level checkpointing that allows the use of different kinds of fast but less reliable storages to reduce the checkpointing frequency to parallel file system (PFS). This paper presents an energy model of multi-level checkpointing and proposes an iterative algorithm that minimizes energy consumption by optimizing the checkpoint interval of each level and selecting the best combination of checkpoint levels. It is confirmed that the algorithm is very fast and effective since it can reach convergence in a relatively small number of iteration steps. This paper also clarifies the fact that it is actually unnecessary to use all the available checkpoint levels in a multi-level CPR mechanism. By selectively using only appropriate checkpoint levels, a significant increase in energy efficiency (9 to 21%) is observed.

At present, most of real-world HPC applications are being developed without considering any auto-tuning techniques; those applications are not "gauto-tunable" for several reasons. One reason is that making a code auto-tunable often results in messing up the code and degrading the readability and/or maintainability. In our previous work, we have employed a code transformation framework, Xevolver, for making a code auto-tunable without messing it up. However, there is no standardized way to express the collaboration between code transformation and auto-tuning. In this paper, therefore, we design a standard tuning scenario and some directives to customize the scenario for individual applications. Our case studies show that the scenario can be reusable among different applications and different auto-tuning techniques by only partially customizing it. As a result, in terms of the number of code lines, the proposed approach requires much less programming effort for achieving auto-tuning.

The Xevolver framework is a code transformation framework for supporting evolutional modifications of high performance computing codes. This paper introduces a set of software modules that facilitates administrative tasks about multiple code transformations on multiple source codes. We call this set of software modules the xevdriver, because it drives transformations using Xevolver framework. First, xevdriver provides an abstract view of temporary files. Parsing and unparsing between Fortran and XML are done automatically, and the user do not have to keep track of temporary file names during a series of applications of code transformations. Second, xevdriver also provides an abstract view of combinations of transformations. Xevdriver provides a script language, in which users can define combinations of code transformations as procedures. Third, the logging functions and a log-viewer are provided in accordance with the above abstractions. Users can check how the source codes are transformed on the log-viewer from the high level abstractions of code transformation procedures, and can inspect the intermediate results down into an arbitrary level of concreteness of the implementations of transformations. Our toolset will help development, management and applications of complex code transformations based on Xevolver framework.

Recently, massively-parallel many-core processors such as Intel Xeon Phi coprocessors have attracted researchers' attentions because various applications are significantly accelerated with those processors. In the field of high-performance computing, OpenMP is a standard programming model commonly used to parallelize a kernel loop for many-core processors. For hierarchical parallel processing, OpenMP version 4.0 or later allows programmers to group threads into multiple thread teams. In this paper, we first show the performance gain of using multiple thread teams even for one many-core processor. Then, we demonstrate that dynamic load balancing among those thread teams has a potential of significantly improving the performance of irregular workloads on a many-core processor. Although the current OpenMP specification does not offer such a dynamic load balancing mechanism, we discuss possible benefits of dynamic load balancing among thread teams through experiments using the Intel Xeon Phi coprocessor.

The Xevolver framework has been developed to enable application programmers to define their own code translation rules outside of their codes so that they can express platform-specific optimizations separately from algorithm-level application codes. Due to the diversity of HPC node architectures, the Xevolver framework has so far mainly been used to separate node-level code optimizations from application codes. However, user-defined code transformation rules are also potentially useful for optimizing MPI applications without messing up their codes. Therefore, this paper shows a case study of using the Xevolver framework to optimize MPI applications through customizable code transformations without loss of high performance portability, and discusses the benefits of the framework.

The appearance of various high-performance computing (HPC) systems compels a user to write a code considering the characteristic of each HPC system. To describe the system-dependent information without drastic code modifications, the directive sets such as the OpenMP directive set and the OpenACC directive set are useful. However, a code becomes complex to achieve high performance on various HPC systems because different directive sets are required for each HPC system. Thus, the code maintainability and readability are degraded. This paper proposes a directive generation approach that generates various kinds of directive sets using user-defined rules. Instead of several kinds of directive sets, a user writes a special placeholder that is utilized to specify a unique code pattern where several directives are inserted. Then, the special placeholder triggers generation of appropriate directives for each system using a user-defined rule with a code translation framework Xevolver. Because only special placeholders are inserted in a code, the proposed approach can keep the code maintainability and readability. From the demonstration of translation into three kinds of directive-based implementations, it is clarified that the proposed approach can replace directives into a smaller number of special placeholders. Moreover, it is clarified that the proposed approach can realize high performance portability by generating appropriate directives for each HPC system.

Sparse Matrix-Vector multiplication (SpMV) is a computational kernel widely used in many applications. There are many different implementations using different processors and algorithms for SpMV. The performances of different SpMV implementations are quite different, and it is basically difficult to choose the implementation that has the best performance for a given sparse matrix and a given platform without performance profiling. This work presents a prototype implementation of an effective machine learning system for SpMV code selection best suited for a given matrix. Instead of using predefined features of a matrix for performance prediction, a feature image and a deep learning network are used to map each sparse matrix to the implementation that has the best performance in advance of the execution. The performance gain by the mechanism is evaluated by using a machine learning method for predicting the best SpMV implementation. According to our evaluation, the proposed mechanism can select an optimal or suboptimal implementation in most cases, though the prediction is not perfect. These results demonstrate the feasibility that the proposed machine learning approach can capture underlying features of an input sparse matrix useful for SpMV code selection.

The last-level cache (LLC) of a modern chip-multiprocessor (CMP) keeps two kinds of data: shared data accessed by multiple cores and private data accessed by only one core. Although the former are likely to have a larger performance impact than the latter, the LLC manages both of those data in the same fashion. To realize a highly efficient execution on a CMP, this paper proposes a cache partitioning mechanism to protect shared data from excessive eviction. The evaluation results show that the proposed mechanism improves the performance by up to 76% and by 8% on average at a cost of less than 2% of the LLC hardware.

This paper proposes a directive translation approach that translates a special placeholder to different directives, depending on the target HPC system. The special placeholder in an application code is used as a trigger for the directive translation. By employing a code translation framework, Xevolver, the special placeholder can be translated to various directives that fit to any target HPC systems. Instead of using multiple directives, it can keep maintainability and readability of the original code because only special placeholders are inserted into an application code. This paper also demonstrates a translation of a special placeholder into OpenMP directives to clarify the effectiveness of the proposed directive translation approach.

Xevolver is a code transformation framework for users to define their own code transformation rules. In the framework, an abstract syntax tree (AST) of an application code is written in an XML format, and its transformation rules are expressed in the XSLT format, which is a standard XML format to describe XML data conversion; an AST and its transformation rules are both written in XML. Since it is too low-level for standard users to manually write XSLT rules, Xevtgen is now being developed as a tool to generate such rules from simple code description. In Xevtgen, users basically write just two code patterns, the original and transformed code patterns. Then, Xevtgen automatically generates a transformation rule that transforms the original code pattern to the transformed one. The generated rule is written in XSLT, and hence usable by other tools of the Xevolver framework. This article shows a use case of using Xevtgen for data layout optimization, and discusses the benefits of using the tool.

P2P (Peer to Peer) has a great potential to handle highly-distributed computing resources and is expected to be a key technology to realize ubiquitous computing environments over the Internet. However, P2P systems tend to waste the network bandwidth for resource acquisition because of their decentralized resource management. This paper presents an efficient control mechanism for self-organizing overlay networks of large-scale P2P systems, and evaluate its performance in detail. The overlay network is configured by making local clusters reflect current interests of individual peers and connecting them together based on their similarity. As a result, the overlay network provides the resource exploitation space for some specific interests. In addition, the overlay network can dynamically be reconfigured based on the change in the interests of individual peers across time so that more useful peers at that time can be reconnected closer to their client peers. Therefore, multicasting of resource requesting messages can be carried out only over peers with similar interests that are dynamically connected through the overlay network, resulting in a remarkable decrease in both messages for resource acquisition and hops a resource requesting query travels to reach the peer that satisfies the request. Experimental results indicate that the proposed mechanism can realize effective self-organization of the overlay network in which useful peers are dynamically relocated around client peers. In addition, the adaptive allocation of links to peers according to their capability works well to keep the higher performance and fault-tolerance of the self-organizing overlay network.

This paper reports a case study of using the Xevolver code transformation framework for data layout optimizations of high-performance computing (HPC) applications. Due to the variety of data structures used in individual applications, a code transformation rule for data layout optimizations is generally specific to a particular application. Since the Xevolver framework enables users to define their own code transformations, a custom code transformation can be defined so that a specific data representation in an existing code can mechanically and consistently be translated to another one. Our evaluation results clearly demonstrate that such a code transformation is effective to improve memory access efficiency and hence the performance of an HPC application without overcomplicating the code.

HPC scientific codes are less readable and less manageable because of complex hand optimization which is often platform-dependent. We are developing a toolset that hopefully mitigates that maintainability problem by user-defined easy-to-use code transformation: The code is written in a simpler form, and coding technique for high performance is introduced by code transformations. In this paper, we present xevtgen, which is a code transformation generator of our toolset. Transformation rules are defined using dummy Fortran codes with some directives, and we expect that design makes it easier to learn for Fortran programmers. Some examples of code transformations are shown to discuss the practicality of the proposed approach.

DRAM-based main memories are energy-hungry components of modern computer systems. Since accesses to DRAM need a complex protocol, the performance of an address-mapping scheme that decides physical locations of data based on physical addresses has a big impact on energy consumption. To improve the energy efficiency, this paper proposes a mechanism that dynamically selects an appropriate address-mapping scheme under the consideration of a trade-off between performance and power consumption. The mechanism works so as to reduce the energy consumption of the main memory. The evaluation results show that the proposed mechanism can reduce the energy consumption in comparison with conventional address-mapping schemes, which do not change their address mappings.

As automatic parallelization functions are different among compilers, a serial code is often modified so that a particular target compiler can easily understand its code structure and data dependency, resulting in effective automatic optimizations. However, these code modifications might not be effective for a different compiler because the different compiler cannot always parallelize the modified code. In this paper, in order to achieve effective parallelization on various HPC systems, compiler messages obtained from various compilers on different HPC systems are utilized for the OpenMP parallelization. Because the message about one system may be useful to identify key loop nests even for other systems, performance portable OpenMP parallelization can be achieved. This paper evaluates the performance of the compiler-assisted OpenMP codes using compiler messages from various compilers. The evaluation results clarified that, when a code is modified for its target compiler, the compiler message given by the target compiler is the most helpful to achieve appropriate OpenMP parallelization.

In standard OpenCL programming, hosts are supposed to control their compute devices. Since compute devices are dedicated to kernel computation, only hosts can execute several kinds of data transfers such as internode communication and file access. These data transfers require one host to simultaneously play two or more roles due to the need for collaboration between the host and devices. The codes for such data transfers are likely to be system-specific, resulting in low portability. This paper proposes an OpenCL extension that incorporates such data transfers into the OpenCL event management mechanism. Unlike the current OpenCL standard, the main thread running on the host is not blocked to serialize dependent operations. Hence, an application can easily use the opportunities to overlap parallel activities of hosts and compute devices. In addition, the implementation details of data transfers are hidden behind the extension, and application programmers can use the optimized data transfers without any tricky programming techniques. The evaluation results show that the proposed extension can use the optimized data transfer implementation and thereby increase the sustained data transfer performance by about 18% for a real application accessing a big data file.

Xevolver is a code transformation framework under active development to help legacy application migration to extreme-scale computing systems. The framework originally assumes that transformation rules are written in XSLT, which might be too low-level for standard users to express their own rules. Hence, this article describes a high-level interface of the Xevolver framework, which offers an easy and declarative way to define a custom compiler directive associated with a composite of predefined loop transformation rules. Such a compiler directive can also be associated with text insertion and deletion. In the evaluation, 160 variants of a triple-nested loop required for empirical performance tuning can be generated mechanically by using the high-level interface.

This paper proposes an extensible programming framework to separate platform-specific optimizations from application codes. The framework allows programmers to define their own code translation rules for special demands of individual systems, compilers, libraries, and applications. Code translation rules associated with user-defined compiler directives are defined in an external file, and the application code is just annotated by the directives. For code transformations based on the rules, the framework exposes the abstract syntax tree (AST) of an application code as an XML document to expert programmers. Hence, the XML document of an AST can be transformed using any XML-based technologies. Our case studies using real applications demonstrate that the framework is effective to separate platform-specific optimizations from application codes, and to incrementally improve the performance of an existing application without messing up the code.

To exploit the potential of many core processors, a serial code is generally optimized for a particular compiler called a target compiler, so that the compiler can understand the code structure for automatic parallelization. However, the performance of such a serial code is always not portable to a new system that uses a different compiler. To improve the performance portability, this paper proposes an OpenMP parallelization method by using compiler messages of the target compiler. Since the compiler messages from the target compiler are also useful to identify key loop nests even for the different system, a programmer can use the message to easily parallelize a serial code with low programming effort. Furthermore, programmer’s intention of the optimization can be migrated to other systems through the OpenMP parallelization, which results in high performance portability. The experimental results indicate that the OpenMP codes parallelized by the proposed method can achieve a comparable or even better performance than the automatically parallelized codes by various compilers.

High-performance computing (HPC) applications have been specialized for their target systems to achieve high performances. Hence, their performances are not portable to other systems. This performance portability problem leads to higher costs for maintaining HPC applications, because the life of an HPC application is usually much longer than that of an HPC system. Therefore, an HPC application needs to be migrated to a new system. Compiler directives can ease such application migration with minor modification of the original code. However, existing compiler directives cannot always satisfy users' requirements. In some cases, customizing the compiler directives for application-specific code transformations is required in order to achieve a high performance as well as high performance portability by using different performance optimizations for individual systems. This paper proposes a mechanism that allows programmers to customize existing compiler directives. To describe the specification of the customized directives, such as directive names, clauses, and their arguments, this paper also presents an XML-based format for customizing directives. The evaluation results show that the proposed approach can customize OpenMP directives to generate multiple code versions that are executed in different ways. With auto-tuning techniques, it is expected that programmers can select the best code version.

A code smell is any part of an application code that might indicate a code or design problem, which makes the application code hard to evolve and maintain. Automatic detection of code smells has been studied to help programmers find which parts of their application codes should be refactored. However, code smells have not been defined in a formal manner. Moreover, existing detection tools are designed for object-oriented applications, but rarely provided for high performance computing (HPC) applications. HPC applications are usually optimized for a particular platform to achieve a high performance, and hence have special code smells called platform-specific code smells (PSCSs). The purpose of this work is to develop a code smell alert system to help programmers find PSCSs of HPC applications to improve the performance portability across different platforms. This paper presents a PSCS alert system that is based on an abstract syntax tree (AST) and XML. Code patterns of PSCSs are defined in a formal way using the AST information represented in XML. XML Path Language (XPath) is used to describe those patterns. The evaluation results obtained by using real applications show that the proposed system can alert potential PSCSs to programmers.

Performance of a serial code often relies on compilers' capabilities for automatic parallelization. In such a case, the performance is not portable to a new system because a new compiler on the new system may be unable to effectively parallelize the ode originally developed assuming a particular target compiler. As the compiler messages from the target compiler are still useful to identify key kernels that should be optimized even for the different system, this paper proposes a method to migrate a serial code to the OpenMP programming model by using such compiler messages. The aim of the proposed method is to improve the performance portability across different systems and compilers. Experimental results indicate that the migrated OpenMP code can achieve a comparable or even better performance than the original code with automatic parallelization.

This paper proposes an OpenCL extension, clMPI, that allows a programmer to think as if GPUs communicate without any help of CPUs. The clMPI extension offers some OpenCL commands of inter-node data transfers that are executed in the same manner as the other OpenCL commands. Thus, clMPI naturally extends the conventional OpenCL programming model so as to improve the MPI interoperability. Unlike conventional joint programming of MPI and OpenCL, CPUs do not need to be blocked to serialize dependent operations of MPI and OpenCL. Hence, an application can easily use the opportunities to overlap parallel activities of CPUs and GPUs. In addition, the implementation details of data transfers are hidden behind the extension, and application programmers can use the optimized data transfers without any tricky programming techniques. As a result, the extension can improve not only the performance but also the performance portability across different system configurations. The evaluation results show that the clMPI extension can use the optimized data transfer implementation and thereby increase the sustained performance by about 14% for the Himeno benchmark if the communication time cannot be overlapped with the computation time.

This article briefly introduces the concept of our new research project, JST CREST “An Evolutionary Approach to Construction of a Software Development Environment for Massively-Parallel Computing Systems.” Since high-performance computing system architectures are going to change drastically, existing application programs will need to evolve for adapting to the new-generation systems. Motivated by this, our project will explore an effective methodology to support the programming for software evolution of valuable existing applications, and also develop a programming framework to bridge the gap between system generations and thereby to encourage migration of existing applications to the new systems. The programming framework will provide abstractions of complicated system configurations at multiple levels, and refactoring tools to help evolving applications to use the abstractions.

Next generation multimedia applications (MMAs) will become a heavy workload for general-purpose processors (GPPs). Although the current single instruction multiple data (SIMD) extensions enable to improve the performance of MMAs, their limited parallel-processing capability is a drawback to execute next generation MMAs in the era of data explosion. This paper proposes an out-of-order vector processing mechanism named OVPM, in order to expand the potential of GPPs on next generation media processing. OVPM can more efficiently utilize memory bandwidth and vector function units than a conventional in-order vector processing mechanism (IVPM), especially for the MMAs with short vectors. The results of performance evaluations using kernels of MMAs show that OVPM achieves a higher performance than that with IVPM.

In this paper, we propose a new transparent checkpoint/restart (CPR) tool, named CheCL, for high-performance and dependable GPU computing. CheCL can perform CPR on an OpenCL application program without any modification and recompilation of its code. A conventional check pointing system fails to checkpoint a process if the process uses OpenCL. Therefore, in CheCL, every API call is forwarded to another process called an API proxy, and the API proxy invokes the API function, two processes, an application process and an API proxy, are launched for an OpenCL application. In this case, as the application process is not an OpenCL process but a standard process, it can be safely check pointed. While CheCL intercepts all API calls, it records the information necessary for restoring OpenCL objects. The application process does not hold any OpenCL handles, but CheCL handles to keep such information. Those handles are automatically converted to OpenCL handles and then passed to API functions. Upon restart, OpenCL objects are automatically restored based on the recorded information. This paper demonstrates the feasibility of transparent check pointing of OpenCL programs including MPI applications, and quantitatively evaluates the runtime overheads. It is also discussed that CheCL can enable process migration of OpenCL applications among distinct nodes, and among different kinds of compute devices such as a CPU and a GPU.

Today, CUDA is the de facto standard programming framework to exploit the computational power of graphics processing units (GPUs) to accelerate various kinds of applications. For efficient use of a large GPU-accelerated system, one important mechanism is checkpoint-restart that can be used not only to improve fault tolerance but also to optimize node/slot allocation by suspending a job on one node and migrating the job to another node. Although several checkpoint-restart implementations have been developed so far, they do not support CUDA applications or have some severe limitations for CUDA support. Hence, we present a checkpoint-restart library for CUDA that first deletes all CUDA resources before check pointing and then restores them right after check pointing. It is necessary to restore each memory chunk at the same memory address. To this end, we propose a novel technique that replays memory related API calls. The library supports both CUDA runtime API and CUDA driver API. Moreover, the library is transparent to applications, it is not necessary to recompile the applications for check pointing. This paper demonstrates that the proposed library can achieve checkpoint-restart of various applications at acceptable overheads, and the library also works for MPI applications such as HPL.

In this paper, we propose a runtime performance prediction model for automatic selection of accelerators to execute kernels in OpenCL. The proposed method is a history-based approach that uses profile data for performance prediction. The profile data are classified into some groups, from each of which its own performance model is derived. As the execution time of a kernel depends on some runtime parameters such as kernel arguments, the proposed method first identifies parameters affecting the execution time by calculating the correlation between each parameter and the execution time. A parameter with weak correlation is used for the classification of the profile data and the selection of the performance prediction model. A parameter with strong correlation is used for building a linear model for the prediction of the kernel execution time by using only the classified profile data. Experimental results clearly indicate that the proposed method can achieve more accurate performance prediction than conventional history-based approaches because of the profile data classification.

Nowadays, multimedia applications (MMAs) form an important workload for general purpose processors. Although the vector architecture is considered the most potential candidate for media processing, the traditional vector architecture has inefficiencies to execute MMAs. This paper proposes a media-oriented vector architecture, which improves the traditional one with a load-forwarding mechanism. The load-forwarding mechanism overcomes the inefficiency on utilization of the memory bandwidth. As a result, the proposed architecture achieves a higher performance with lower hardware cost than the traditional one. This paper evaluates the proposed architecture with architectural design parameters and finds out the most efficient size for the vector architecture when performing MMAs.

Peer to peer (P2P) systems are extremely vulnerable to Sybil attacks, in which a malicious user controls a large number of Sybil peers to collude to break the system laws. This paper proposes a distributed algorithm, named Sybil Resisting Network Clustering (SRNC), to resist the Sybil attack by preventing honest peers from communicating with Sybil Peers. SRNC is based on a social network model. In this model, honest peers and Sybil peers can be largely classified into two clusters, connected by a small number of edges, called attack edges. SRNC tries to explicitly detect attack edges, and then prohibits the communication over the detected edges. The performance of SRNC is evaluated by theoretical analysis and simulations. In particular, SRNC ensures theoretically that honest peers totally accept O(jAEj) Sybil peers. This is a O(log(n)) times improvement over SybilLimit, one of the conventional representative Sybil resisting algorithms, where n is the number of peers and jAEj is the number of attack edges in the system. The performance is then evaluated by simulations on data sets of real world social networks.

In this paper, a tool named CheCUDA is designed to checkpoint CUDA applications that use GPUs as accelerators. As existing checkpoint/restart implementations do not support checkpointing the GPU status, CheCUDA hooks a part of basic CUDA driver API calls in order to record the status changes on the main memory. At checkpointing, CheCUDA stores the status changes in a file after copying all necessary data in the video memory to the main memory and then disabling the CUDA runtime. At restarting, CheCUDA reads the file, re-initializes the CUDA runtime, and recovers the resources on GPUs so as to restart from the stored status. This paper demonstrates that a prototype implementation of CheCUDA can correctly checkpoint and restart a CUDA application written with basic APIs. This also indicates that CheCUDA can migrate a process from one PC to another even if the process uses a GPU. Accordingly, CheCUDA is useful not only to enhance the dependability of CUDA applications but also to enable dynamic task scheduling of CUDA applications required especially on heterogeneous GPU cluster systems. This paper also shows the timing overhead for checkpointing.

In Grid Computing, harnessing the power of idle resources in a distributed environment is one of the important features. However, to fully benefit from this computing model, an appropriated resource allocation method needs to be carefully chosen and deployed. A number of studies have been done on this area and one of the promising approaches is to adopt a marketing scheme called the auction model, which has been drawing much attention during past several years. In this paper, we propose a new utility-aware resource allocation protocol to make external scheduling decision in Grid. Users and service providers specify one or more weight values, and then, an auctioneer uses these values for calculating both userspsila and service providerspsila utility values which reflect preference upon the matched members in the different group. Then, we map the scheduling problem with these utility values into the problem in a weighted bipartite graph, and propose a new matching algorithm based on the existing SMP (Stable Marriage Problem) matching algorithm. Finally, the performance of this auctionpsilas awarding technique is evaluated.

A commodity personal computer (PC) can be seen as a hybrid computing system equipped with two different kinds of processors, i.e. CPU and a graphics processing unit (GPU). Since the superiorities of GPUs in the performance and the power efficiency strongly depend on the system configuration and the data size determined at the runtime, a programmer cannot always know which processor should be used to execute a certain kernel. Therefore, this paper presents a runtime environment that dynamically selects an appropriate processor so as to improve the energy efficiency. The evaluation results clearly indicate that the runtime processor selection at executing each kernel with given data streams is promising for energy-aware computing on a hybrid computing system.

This paper proposes an algorithm for self-organization of an overlay network to efficiently search appropriate computing resources in a large-scale grid computing environment. To reduce redundant links and the point of failure, this logical link reconnection algorithm considers the resource usage order of individual peers. Experimental results show that the retrieval efficiency can be increased by 20% in comparison with the previous algorithm. Therefore, in the ubiquitous computing environment, flooding search packets can be reduced while keeping the same performance of resource discovery.

Large scale volunteer computing has been proved to be an efficient mechanism to solve the complicated problems. Specifically, in such a system, thousands of idle computers on the network are organized to finish a series of tasks dispatched by a central server. However, this computing model is vulnerable to attack from malicious peers returning incorrect results, since it is impossible to check each of thousands of the results. To address this problem, we propose a scheme to evaluate the reliability of each peer, and hence to distinguish whether the peer is honest or malicious. Specifically, the task dispatching pattern is changed so that the results returned from a peer can reflect the type of this peer. We focus on a typical dispatching pattern, and analyze its performance both theoretically and experimentally. The results indicate that the proposed scheme can effectively differentiate the malicious peers for most of the reasonable situations.

This article examines the potential of the Cell processor as a platform for secure data mining on the future volunteer computing systems. Volunteer computing platforms have the potential to provide massive computing power. However, privacy and security concerns prevent using volunteer computing for data mining of sensitive data. The Cell processor comes with hardware security features. The secure volunteer data mining can be achieved by using those hardware security features. In this article, we present a general security scheme for the volunteer computing, and a secure parallelized K-Means clustering algorithm for the Cell processor. We also evaluate the performance of the algorithm on the Cell secure system simulator. Evaluation results indicate that the proposed secure data clustering outperforms a non-secure clustering algorithm on the general purpose CPU, but incurs a huge performance overhead introduced by the decryption process of the Cell security features. Possible optimization for the secure K-Means clustering is discussed.

This paper proposes a P2P-based dynamic load balancing mechanism to increase the dependability of volunteer computing. The proposed mechanism is incorporated into a volunteer computing middleware, called the Berkeley Open Infrastructure for Network Computing (BOINC). The proposed mechanism provides two additional features: decentralized load balancing and proxy download. The former feature reduces the variation of the execution times for individual tasks, which are usually aggravated by dynamic and unpredictable load changes on volunteer computing resources. The latter offers another way to assign tasks to idle computing resources when the BOINC project server fails in the task assignment. Using a prototype implementation, this paper examines the effect of the proposed mechanism on the performance of a real volunteer computing system. The experimental results show that the proposed mechanism can reduce the maximum turnaround time by 42% and further improve the total throughput of the volunteer computing system by 27%.