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In conclusion, the papers collected in this Special Issue summarize significant advances in the field of optical sensors, with specific contributions in sensor technology and applications of fiber Bragg gratings, resonators and spectroscopy. The performance of this integrated sensor is demonstrated using glucose solutions (0.05-0.3 g/mL) and the sensor response is shown to be dynamic and reversible. The refractive index sensor exhibits a linear response in the refractive index range of 1.333-1.358 RIU (refractive index unit), with a sensitivity of 32.4 RIU SP -1 sp and a resolution of 2 × 10 SP -3 sp RIU at the refractive index of water. Today, optical sensors are the subject of a very significant number of studies and applications. [Extracted from the article]

OLEDoS displays hold great promise for AR/VR applications, but the ultra‐high pixel density required for microdisplays, exceeding several thousand PPI, presents significant challenges for pixel circuit design. Above all, the maximum OLED current of each OLEDoS sub‐pixel is extremely low, on the order of several nanoamperes or less, resulting in a data voltage range narrower than a few hundred millivolts. Consequently, for example, when expressing 10‐bit grayscale, designing data driver circuits to divide the data voltage range into 1,024 levels becomes exceedingly challenging. Furthermore, circuit techniques that compensate for variations in transistor characteristics are nearly inapplicable due to the ultra‐small pixel area. This paper proposes a pixel circuit design method to expand the data voltage range for a 4,670‐PPI OLEDoS display while considering luminance uniformity. The effectiveness of the proposed pixel circuit was verified through measurements on 40×120 pixel arrays fabricated in a 5V 0.13μm CMOS process. [ABSTRACT FROM AUTHOR]

Objective: Early stage diagnosis of sepsis without overburdening health services is essential to improving patient outcomes. Methods: A fast and simple-to-use platform that combines an integrated circuit with paper microfluidics for simultaneous detection of multiple-metabolites appropriate for diagnostics was presented. Paper based sensors are a primary candidate for widespread deployment of diagnostic or test devices. However, the majority of devices today use a simple paper strip to detect a single marker using the reflectance of light. However, for many diseases such as sepsis, one biomarker is not sufficient to make a unique diagnosis. In this work multiple measurements are made on patterned paper simultaneously. Using laser ablation to fabricate microfluidic channels on paper provides a flexible and direct approach for mass manufacture of disposable paper strips. A reusable photodiode array on a complementary metal oxide semiconductor chip is used as the transducer. Results: The system measures changes in optical absorbance in the paper to achieve a cost-effective and easily implemented system that is capable of multiple simultaneous assays. Potential sepsis metabolite biomarkers glucose and lactate have been studied and quantified with the platform, achieving sensitivity within the physiological range in human serum. Conclusion: We have detailed a disposable paper-based CMOS photodiode sensor platform for real-time simultaneous detection of metabolites for diseases such as sepsis. Significance: A combination of a low-cost paper strip with microfluidic channels and a sensitive CMOS photodiode sensor array makes our platform a robust portable and inexpensive biosensing device for multiple diagnostic tests in many different applications. [ABSTRACT FROM AUTHOR]

This paper presents folded cascode Low Noise Amplifier (LNA) designed for Wireless Local Area Network (WLAN) applications. The proposed LNA uses complementary current reuse technique and diode connected forward body biasing technique to lower the power consumption and boost the transconductance for gain enhancement. Moreover, post linearization is done by P-MOS (Metal Oxide Semiconductor) Inter Modulation Distortion (IMD) sinker which reduces inter modulation distortion present at the input and achieves better linearity of the LNA. Under cadence virtuoso environment, using 180 nm Complementary Metal Oxide Semiconductor (CMOS) technology, the designed LNA exhibit high gain (S21) of 25.4 dB followed by noise figure of 1.75 dB at a reduced supply voltage of 0.6 V. The other important parameters including reflection coefficient (S11) − 12 dB, power dissipation (Pdc) 3.23 mW and Third order Input Intercept Point (IIP3) − 4.43 dBm are also achieved. This demonstrates the applicability of proposed LNA for wireless applications functioning in 5.2 GHz. [ABSTRACT FROM AUTHOR]

MicroIC enables display attributes unattainable from polycrystalline thin‐film transistors, and the complimentary metal‐oxide semiconductor (CMOS) microICs support a wide range of applications beyond driving pixels. Integrating sensors within displays can add value to products, reduce costs and improve performance versus conventional solutions. As evidenced by touch and display integration in mobile displays via TDDI ICs, in‐cell sensing can reduce cost and improve performance to levels that are not available with all display types. Capacitive touch, optical touch, 3D scanning, and proximity sensing can also benefit from the inherent coordination between sensors and display. We present multiple sensing architectures and demonstrations of integration within microLED displays and describe CMOS microIC circuits for touch sensing applications. With diverse heterogenous semiconductor technology tightly woven into displays, the potential for intuitive gesture controls, adaptive interfaces, and enhanced sensory feedback paves the way for more natural and effortless interactions between humans and machines. [ABSTRACT FROM AUTHOR]

This paper described the new system of biosensing using CMOS chip. The system was expected to be used in various circumstances because it was suitable for miniaturization compared to the conventional system. To conduct electrochemical measurements, the new system used paper fluidic channel set on the CMOS chip to transport solution to the on-chip electrodes. The materials of paper fluidic channel were only paper and silicone resin, and these were biocompatible. In experiment, we carried out simultaneous detection of glucose and ethanol in liquid sample solutions on the 5mm square CMOS chip and paper fluidic channel. Furthermore, this system can detect various target molecules in addition to glucose and ethanol, and increase number of simultaneous measurement by adding some more process to the paper and CMOS chip. [ABSTRACT FROM AUTHOR]

This paper proposes a digital delay locked loop (DLL) with a monotonic delay line (DL). This DLL adopts the calibration mode to reduce the non‐monotonic effects for the coarse‐tuning delay line (CTDL) and the fine‐tuning delay line (FTDL). The calibration mode detects the delay time of the delay unit, the timing resolution of CTDL, to adjust the delay range of the FTDL. Thus, the calibration mode can limit the overlap range of the delay time between the CTDL and the FTDL. The proposed DLL was implemented using a 0.18‐μm CMOS process, and the RMS and the peak‐to‐peak jitters of the DLL were 0.21% and 1.72%, respectively, at 560 MHz. [ABSTRACT FROM AUTHOR]

An unconventional portable electrochemical gas sensor composed of a smartphone, a fingersized sensing chip and a single use paper-based enzyme electrode was proposed to detect a particular target gaseous inclusion for self-breath-analysis with ease. This attempt allowed us to monitor our physical status immediately and continuously regardless of a time, place or person due to the improved convenience, immediacy, and affordability. The custom CMOS chip with the capability of performing an amperometric determination when the power voltage supplied from the earphone jack of a smartphone was designed as an analytical device. A disposable enzyme electrode was prepared simply from a chromatography paper and a commercial carbon pencil instead of the conventional indisposable material and complex manufacturing process. The quantification of ethanol in gaseous samples was demonstrated in range from 50 to 500ppm (V/V) in accord with concentrations in exhaled breath. The response current increased linearly with increasing vapor ethanol concentration. [ABSTRACT FROM AUTHOR]

This paper presents a low cost portable medical device for biochemical sensor using CMOS chip and paper-based fluidic channel. We measured a potential produced by enzyme activity of glucose between the working and reference electrode on CMOS chip. A liquid sample is transported by paperbased fluidic channel, which is made of chromatography paper and silicone resin, and consists of the area for filtering a sample (filter layer) and that for reacting enzyme (enyzme layer). The paper-based fluidic channel is used by combining CMOS chip, and the solution with glucose is dropped from top of the paperbased fluidic channel. The concentrations of glucose are detected by potentiometry (open circuit potential time). The experimental results show that the glucose concentration is measured by CMOS chip and paper-based fluidic channel. [ABSTRACT FROM AUTHOR]

The increasing demand for high-density Very Large-Scale Integrated (VLSI) circuits, driven by the scaling of CMOS technology, is primarily challenged by the need for uniformity in SRAM cells. Given that most programs frequently seek dependable data, the primary cache and memory caching (MC) component in SRAM tends to be relatively steady. Resolving power and delay imbalances is the main problem with SRAM cells. The issues with CMOS-based SRAM cells include high cost, wide parameter variation, and worse dependability. CMOS devices also experience a loss of channel control by the gate. It is therefore advised to use FinFET-based SRAM cells rather than CMOS. This paper presents a design study of a 1T-1D SRAM cell using FinFET and CMOS technology. Without changing the logic state of the SRAM cell, the objective of this paper is to lessen power leakage. The cell structure's ease of design also contributes to its remarkable affordability and accessibility. A 1T-1D cell with the bare minimum of transistors has a smaller overall area. The suggested 1T-1D SRAM cell is implemented using the Tanner EDA working platform, which uses 7nm FinFET technology. With this study, low power was reached up to 99%, and delay reduction was improved to 98%. [ABSTRACT FROM AUTHOR]

Video processing is the most emergent area of image processing in Research and Development. This paper, we present some advanced technology interrelated to video and image processing, which will provide a super-resolution high-quality most prominent visible light video for better human visualization and background motions or gesticulations of the human brain. There are two approaches for increasing the current resolution level of an image. The first one is the improvement of spatial resolution by reducing the size of pixels through the techniques of sensor manufacturing by about 40 $ {\mathcal{M}}{\textrm{m}^2} $ M m 2 for a 0.35 $ {\mathcal{M}}\textrm{m} $ M m CMOS process and the second approach is the enhancement of chip size that also enhances the capacitance. In video processing, we mainly focus on object images, i.e. any form of signal processing in which the input is an image and the output is a photograph or a frame of video. So, it will be better to converge over techniques of digital image processing. In the proposed algorithm (MHI Simulink model), edge extraction is performed to find the precious area of MRI and CT-Scan images. Using FPGA, edge detection methods have been implemented over scanned images to get better accuracy. The accuracy of the proposed method has been compared with Prewitt and Sobel's edge detection techniques. The proposed method has given better accuracy than Prewitt and Sobel methods. Finally, this paper shows future directions for researchers to enhance the characteristics of digital image and video processing. [ABSTRACT FROM AUTHOR]

This document is a summary of an article titled "Abridging the CMOS Technology II" published in the journal Nanomaterials. The article discusses the advancements in nanosheet, forksheet, and CFET device structures, as well as 3D stacking techniques, that are expected to extend the lifespan of silicon CMOS devices. It also explores the challenges of achieving integration of 2D material ICs and the potential of innovative 2D materials for the future of integrated electronics. The article includes several review papers and regular papers on topics such as contact scaling, reliability concerns of FinFETs, carrier distribution in 2D quantized metal/insulator transition regions, flash memory technology, ZnO-based thin-film transistors, ESD protection strategies, and device innovation with emerging 2D semiconductor materials. The article concludes by stating that CMOS technology will remain the predominant integration technology for the foreseeable future, and the integration of innovative 2D materials into CMOS processes is expected to drive the next leap in technological advancement. [Extracted from the article]

Abstract: This paper discusses recent progress in and challenges of threshold voltage control for advanced high-k/metal-gated (HKMG) devices. It presents the impact on threshold voltage (V t) control of incorporating La and Al into HKMG devices. A dipole moment model explaining V t tuning of HfSiON/metal-gated MOSFETs is proposed. In addition, a dual channel scheme that allows La2O3 capping in NMOS and a SiGe channel in PMOS to achieve acceptable V t for HKMG CMOS devices will be discussed. Also shown is the impact of the robustness of the SiO2/Si interface on the HKMG MOSFET V t-equivalent oxide thickness (EOT) roll-off. Finally, techniques to improve the interface quality of a HKMG stack will be discussed. [Copyright &y& Elsevier]

Abstract: Ge CMOS is very attractive for the post size-scaled Si-CMOS. However, we have to tackle a number of challenges with regard to materials and their interface control. In this paper, we discuss gate stack formation and source/drain engineering, as well as their implications for the performance of n- and p-MOSFETs. Because the Ge interface is significantly degraded by the GeO desorption occurring at a relatively low temperature (∼500°C), it is very hard to control Ge gate stack formation by a simple thermal budget control. In addition, strong Fermi-level pinning at the Ge/metal interface is a big problem in source/drain engineering. After discussing ways to control this desorption and Fermi-level pinning at the interface in both p-FETs and n-FETs, we discuss our current status of both electron and hole mobilities. [Copyright &y& Elsevier]

Abstract: The down-scaling is still the most important and effective way for achieving the high-performance logic CMOS operation with low power, regardless of its concern for the technological difficulties, and thus, the past shrinking trend of the gate-length has been very aggressive. In this paper, logic CMOS technology roadmap for ‘22nm and beyond’ is described with ITRS (International Technology Roadmap for Semiconductor) as a reference. In the ITRS 2008 Update published just recently, there has been some significant change in the trend of the gate length. The future gate-length shrinking trend predicted in the past several versions of the ITRS has been too aggressive even for the most advanced semiconductor companies to catch up, and thus, the predicted trend has been amended to be less aggressive from the ITRS 2008 Update, resulting in the delay in the gate-length shrinkage for 3years in the short term and 5years in the long term from those predicted in ITRS 2007. Corresponding to this, the pace of the introduction of new technologies becomes slower. For the long term, the limit of the downsizing is a big concern. The limit is expected to be at the gate length of around 5nm because of the too huge off-leakage current in the entire chip. Until that we will have probably six more generations or ‘technology nodes’, considering that we are now in the so-called 45nm generation. It would take probably 20–30years until we reach the final limit, because the duration between the generations will become longer when approaching the limit. In order to suppress the off-leakage current, double gate (DG) or fin-FET type MOSFETs are the most promising. Then, it is a natural extension for DG FETs to evolve to Si-nanowire MOSFETs as the ultimate structure of transistors for CMOS circuit applications. Si-nanowire FETs are more attractive than the conventional DG FETs because of higher on-current conduction due to their quantum nature and also because of their adoptability for high-density integration including that of 3D. Then, what will come next after reaching the final limit of the downsizing? The answer is new algorithm. In the latter half of this century, the application of algorithm used for the natural bio system such as the brains of insects and even human will make the integrated circuits operation tremendously high efficiency. Much higher performance with ultimately low power consumption will be realized. [Copyright &y& Elsevier]

An introduction is presented in which the editor discusses various reports within the issue on topics including complementary metal oxide semiconductor (CMOS), analog-to-digital converters and digital electronics.

A 13.3‐in. UHD LTPS TFT‐LCD with MUX3 by 15Hz driving was demonstrated in this paper. Since the high mobility of LTPS TFT and good design rule, the aperture ratio could be improved 28% compared to a‐Si. By 15Hz driving, the logical power can be saved 34%. The total power of 13.3‐in. UHD TFT‐LCD could be lower to 2.7W by LTPS technology. The cell border could be easily down to 1.0mm by small TFT design and the down border could be down to 6.8mm with two 1932ch IC by MUX3 design. [ABSTRACT FROM AUTHOR]

Transistor random threshold voltage variations due to process fluctuations seriously affects the stability of Static Random Access Memory (SRAM). In this paper, a SRAM bit transistors threshold voltage $({Vth})$ deviation monitoring scheme and system is proposed. This scheme ingeniously achieves on-chip measurement of all transistors threshold voltages without altering compact SRAM bit array layout. Control signal strategies and Transistor ${Vth}$ Determination Circuit (TVDC) for different types of Devices Under Test (DUTs) have been proposed. The system is implemented using a 65 nm CMOS process with a core area of 0.01875mm2. Through Monte Carlo analysis, the Weighted Average (WA) difference of the proposed scheme and the direct measurement method is not more than 10mV, and the Root Mean Square Error (RMSE) difference is not more than 3mV. This system can also effectively detect the cell position of the transistor threshold voltage mismatch simulated by modifying the substrate voltage. For SRAM arrays of different scales, the method proposed in this paper has area efficiency and flexible reconfigurability. [ABSTRACT FROM AUTHOR]

Although the von Neumann architecture-based computing system has been used for a long time, its limitations in data processing, energy consumption, etc. have led to research on various devices and circuit systems suitable for logic-in-memory (LiM) computing applications. In this paper, we analyze the temperature-dependent device and circuit characteristics of the floating gate field effect transistor (FGFET) source drain barrier (SDB) and FGFET central shallow barrier (CSB) identified in previous papers, and their applicability to LiM applications is specifically confirmed. These FGFETs have the advantage of being much more compatible with existing silicon-based complementary metal oxide semiconductor (CMOS) processes compared to devices using new materials such as ferroelectrics for LiM computing. Utilizing the 32 nm technology node, the leading-edge node where the planar metal oxide semiconductor field effect transistor structure is applied, FGFET devices were analyzed in TCAD, and an environment for analyzing circuits in HSPICE was established. To seamlessly connect FGFET-based devices and circuit analyses, compact models of FGFET-SDB and -CSBs were developed and applied to the design of ternary content-addressable memory (TCAM) and full adder (FA) circuits for LiM. In addition, depression and potential for application of FGFET devices to neural networks were analyzed. The temperature-dependent characteristics of the TCAM and FA circuits with FGFETs were analyzed as an indicator of energy and delay time, and the appropriate number of CSBs should be applied. [ABSTRACT FROM AUTHOR]

For processing streaming events from a Dynamic Vision Sensor camera, two types of neural networks can be considered. One are spiking neural networks, where simple spike-based computation is suitable for low-power consumption, but the discontinuity in spikes can make the training complicated in terms of hardware. The other one are digital Complementary Metal Oxide Semiconductor (CMOS)-based neural networks that can be trained directly using the normal backpropagation algorithm. However, the hardware and energy overhead can be significantly large, because all streaming events must be accumulated and converted into histogram data, which requires a large amount of memory such as SRAM. In this paper, to combine the spike-based operation with the normal backpropagation algorithm, memristor–CMOS hybrid circuits are proposed for implementing event-driven neural networks in hardware. The proposed hybrid circuits are composed of input neurons, synaptic crossbars, hidden/output neurons, and a neural network's controller. Firstly, the input neurons perform preprocessing for the DVS camera's events. The events are converted to histogram data using very simple memristor-based latches in the input neurons. After preprocessing the events, the converted histogram data are delivered to an ANN implemented using synaptic memristor crossbars. The memristor crossbars can perform low-power Multiply–Accumulate (MAC) calculations according to the memristor's current–voltage relationship. The hidden and output neurons can convert the crossbar's column currents to the output voltages according to the Rectified Linear Unit (ReLU) activation function. The neural network's controller adjusts the MAC calculation frequency according to the workload of the event computation. Moreover, the controller can disable the MAC calculation clock automatically to minimize unnecessary power consumption. The proposed hybrid circuits have been verified by circuit simulation for several event-based datasets such as POKER-DVS and MNIST-DVS. The circuit simulation results indicate that the neural network's performance proposed in this paper is degraded by as low as 0.5% while saving as much as 79% in power consumption for POKER-DVS. The recognition rate of the proposed scheme is lower by 0.75% compared to the conventional one, for the MNIST-DVS dataset. In spite of this little loss, the power consumption can be reduced by as much as 75% for the proposed scheme. [ABSTRACT FROM AUTHOR]

Abstract: Flash memory, in particular NAND, has been an enabling technology for portable applications for the last two decades. The strength of Flash is its excellent scaling capability, allowing an ever increasing density at a decreasing cost and maintained reliability. However, the geometrical scaling of the cell exacerbates charge loss and fluctuation effects. On the other hand, new post-Flash memory technologies are being proposed, with different storage concepts and reliability physics. This review discusses the major reliability issues for Flash, with emphasis on the physical mechanisms and modeling. The reliability of charge trap and resistive memories, such as phase change and resistive switching memories, is addressed. [Copyright &y& Elsevier]

Abstract: The unwanted high threshold voltage (Vt ) is the major challenge for metal-gate/high-κ CMOS especially at small equivalent-oxide-thickness (EOT). We have investigated the high Vt issue that is due to flat-band voltage (Vfb ) roll-off at smaller EOT. A mechanism of charged oxygen vacancies formed by interface reaction was proposed to explain the Vfb roll-off effect. This interface reaction can be decreased by inserting a thin interfacial SiON and using novel low temperature process. The self-aligned and gate-first metal-gate/high-κ CMOSFETs using these methods have achieved low Vt and good control of Vfb roll-off at small 0.6–1.2nm EOT. [Copyright &y& Elsevier]

HfO 2 -based thin films have raised considerable interest in ferroelectric memory devices due to their thickness scalability and process compatibility with CMOS. Stress exhibits a significant influence on ferroelectric polarization in HfO 2 -based films. However, the effect of stress has yet to be clarified despite numerous efforts, and there has been a lack of systematic review to collate and discuss this effect. This paper briefly introduces how stress is characterized in HfO 2 -based polycrystalline films as basis. Then, the process in which stress affects ferroelectricity is carefully discussed. The paper subsequently elaborates both the effects of out of plane stress and in plane stress. Furthermore, the interaction between stress and other factors is presented. Finally, the up-to-date research on the effect of stress are summarized, and several further research challenges for researchers are provided. Given the ubiquitous stress during the chip manufacturing process, a detailed summary of the stress effect has technological implications for processing and applications of HfO 2 -based thin films. [ABSTRACT FROM AUTHOR]

In this paper, a double-pole double-throw analog switch with n-channel architecture driven by a charge pump is described. The architecture proposed in this paper not only can reduce the on-resistance of the complementary metal oxide semiconductor (CMOS) switch, but also can realize a stable on-resistance within the full swing range of the input signal. This analog switch has the characteristics of high-speed, low-voltage, and high linearity, which is suitable for high-speed USB (Universal Serial Bus) 2.0 applications and meets low-speed and full-speed USB requirements. The test chip using a 0.25 μm BCD (bipolar–CMOS–DMOS) process confirms the characteristics of the switch. It uses + 2.8 to + 5.5 V single power supply, and the normal operating temperature range is − 40 to + 85 °C. This switch has an over-voltage protection function, which can prevent damage to the switch from the high input voltage. Besides, the switch port can realize dual-direction transmission. The analog switch designed in this paper solves some problems of traditional analog switches, such as large on-resistance, large supply current, and large parasitic capacitance. The on-resistance of the analog switch architecture in this paper is 5 Ω and the on-resistance flatness is 0.1 Ω. The supply current is as low as 0.87 μA while the whole chip area is 0.65 mm2. [ABSTRACT FROM AUTHOR]

In this paper, we propose the use of punch-through nMOS (PTnMOS) as an alternative to pMOS in complementary metal oxide semiconductor (CMOS) circuits. According to the TCAD simulation results, PTnMOS exhibit sub-threshold characteristics similar to those of pMOS and can be formed by simply changing the doping concentration of the source and drain. Without the need for sizing, which solves the area occupation problem caused by the need to increase the width of pMOS due to insufficient hole mobility. In addition, we compose a PTnMOS and nMOS without sizing to form a single-carrier CMOS in which only electrons are transmitted, and We extract its performance for comparison with conventional CMOS (Wp/Wn = 1). The results indicate that single-carrier CMOS has symmetric noise margin and 29% faster delay time compared to conventional CMOS (Wp/Wn = 1). If III–V or II–VI group materials could be applied to single-carrier CMOS, not only could costs be reduced and wafer area occupancy minimized, but also significant improvements in the performance and bandwidth application of microwave circuits could be achieved. [ABSTRACT FROM AUTHOR]

This paper presents a charge pump circuit with a wide output range and low current mismatch applied to phase-locked loops. In this designed structure, T-shaped analog switches are adopted to suppress the non-ideal effects of clock feedthrough, switching time mismatch, and charge injection. A source follower and current splitting circuits are proposed to improve the matching accuracy of the charging and discharging currents and reduce the current mismatch rate. A rail-to-rail high-gain amplifier with a negative feedback connection is introduced to suppress the charge-sharing effect of the charge pump. A cascode current mirror with a high output impedance is used to provide the charge and discharge currents for the charge pump, which not only improves the current accuracy of the charge pump but also increases the output voltage range. The proposed charge pump is designed and simulated based on a 65 nm CMOS process. The results show that when the power supply voltage is 1.2 V, the output current of the charge pump is 100 μA, the output voltage is in the range of 0.2~1 V, and the maximum current mismatch rate and current variation rate are only 0.21% and 1.4%, respectively. [ABSTRACT FROM AUTHOR]

Purpose: Based on the micro-electro-mechanical system (MEMS) technology, acoustic emission sensors have gained popularity owing to their small size, consistency, affordability and easy integration. This study aims to provide direction for the advancement of MEMS acoustic emission sensors and predict their future potential for structural health detection of microprecision instruments. Design/methodology/approach: This paper summarizes the recent research progress of three MEMS acoustic emission sensors, compares their individual strengths and weaknesses, analyzes their research focus and predicts their development trend in the future. Findings: Piezoresistive, piezoelectric and capacitive MEMS acoustic emission sensors are the three main streams of MEMS acoustic emission sensors, which have their own advantages and disadvantages. The existing research has not been applied in practice, and MEMS acoustic emission sensor still needs further research in the aspects of wide frequency/high sensitivity, good robustness and integration with complementary metal oxide semiconductor. MEMS acoustic emission sensor has great development potential. Originality/value: In this paper, the existing research achievements of MEMS acoustic emission sensors are described systematically, and the further development direction of MEMS acoustic emission sensors in the future research field is pointed out. It provides an important reference value for the actual weak acoustic emission signal detection in narrow structures. [ABSTRACT FROM AUTHOR]

A power-efficient 16-bit 1-MS/s successive approximation register (SAR) analog-to-digital converter (ADC) is presented in this paper. High-bit sampling makes the bridge capacitance in the digital-to-analog converter (DAC) a unit one, eliminating fractional capacitance mismatch. The high-precision comparator is composed of a four-stage preamplifier and a strong-arm latch, with auto-zeroing used to mitigate input offset further. Digital foreground calibration based on low-bit weight is implemented to correct DAC capacitance mismatch. The post-layout simulation results show that the core ADC achieves 95.61 dB SNDR and 105.1 dB SFDR with calibration, consuming 5.4 mW power under a 3.3 V supply voltage, corresponding to a Schreier figure of merit (FoM) of 175.3 dB. The ADC core area is 1.06 mm2 in the 180 nm CMOS technology. [ABSTRACT FROM AUTHOR]

Deep-brain stimulation (DBS) is a highly effective and safe medical treatment that improves the lives of patients with a wide range of neurological and psychiatric diseases. It has been established as a first-line tool in the treatment of these conditions for the past two decades. Closed-loop deep-brain stimulation (CLDBS) advances this tool further by automatically adjusting the stimulation parameters in real time based on the brain's response. In this context, this paper presents a low-noise amplifier (LNA) and a neurostimulator circuit fabricated using the low-power/low-voltage 65 nm CMOS process from TSMC. The circuits are specifically designed for implantable applications. To achieve the best tradeoff between input-referred noise and power consumption, metaheuristic algorithms were employed to determine and optimize the dimensions of the LNA devices during the design phase. Measurement results showed that the LNA had a gain of 41.2 dB; a 3 dB bandwidth spanning over three decades, from 1.5 Hz to 11.5 kHz; a power consumption of 5.9 µW; and an input-referred noise of 3.45 µVRMS, from 200 Hz to 11.5 kHz. The neurostimulator circuit is a programmable Howland current pump. Measurements have shown its capability to generate currents with arbitrary shapes and ranging from −325 µA to +318 µA. Simulations indicated a quiescent power consumption of 0.13 µW, with zero neurostimulation current. Both the LNA and the neurostimulator circuits are supplied with a 1.2 V voltage and occupy a microdevice area of 145 µm × 311 µm and 88 µm × 89 µm, respectively, making them suitable for implantation in applications involving closed-loop deep-brain stimulation. [ABSTRACT FROM AUTHOR]

Ambient light sensors are becoming increasingly popular due to their effectiveness in extending the battery life of portable electronic devices. However, conventional ambient light sensors are large in area and small in dynamic range, and they do not take into account the effects caused due to a dark current. To address the above problems, a programmable ambient light sensor with dark current compensation and a wide dynamic range is proposed in this paper. The proposed ambient light sensor exhibits a low current power consumption of only 7.7 µA in dark environments, and it operates across a wide voltage range (2–5 V) and temperature range (−40–80 °C). It senses ambient light and provides an output current proportional to the ambient light intensity, with built-in dark current compensation to effectively suppress the effects of a dark current. It provides a wide dynamic range over the entire operating temperature range with three selectable output-current gain modes. The proposed ambient light sensor was designed and fabricated using a 0.18 µm standard CMOS process, and the effective area of the chip is 663 µm × 652 µm. The effectiveness of the circuit was verified through testing, making it highly suitable for portable electronic products and fluorescent fiber-optic temperature sensors. [ABSTRACT FROM AUTHOR]

This paper introduces an innovative method for the analysis of alcohol–water droplets on a CMOS capacitive sensor, leveraging the controlled thermal behavior of the droplets. Using this sensing method, the capacitive sensor measures the total time of evaporation (ToE), which can be influenced by the droplet volume, temperature, and chemical composition. We explored this sensing method by introducing binary mixtures of water and ethanol or methanol across a range of concentrations (0–100%, with 10% increments). The experimental results indicate that while the capacitive sensor is effective in measuring both the total ToE and dielectric properties, a higher dynamic range and resolution are observed in the former. Additionally, an array of sensing electrodes successfully monitors the droplet–sensor surface interaction. However practical considerations such as the creation of parasitic capacitance due to mismatch, arise from the large sensing area in the proposed capacitive sensors and other similar devices. In this paper, we discuss this non-ideality and propose a solution. Also, this paper showcases the benefits of utilizing a CMOS capacitive sensing method for accurately measuring ToE. [ABSTRACT FROM AUTHOR]

In this paper we present User Customizable Logic Paper (UCLP) with a Sea-of Transmission-Gates (SOTG) of 2-V organic CMOS transistors. This can enable users to fabricate custom integrated circuits, by printing 200 \mu\ m wide interconnects with at-home ink-jet printers for the prototyping of large-area electronics and educational purposes. The SOTG reduces the area of the circuits in UCLP by between 11% and 85% compared with a conventional gate array architecture. [ABSTRACT FROM AUTHOR]

The article invites, papers from authors for a special issue of the journal "IEEE Transactions on Electron Devices" on "Reliability of CMOS Logic, Memory, Power and Beyond CMOS Devices."

The article presents the invitation of the journal to interested individuals to submit papers and articles on memory, logic and CMOS devices.

The technology of CMOS‐compatible Single Photon Avalanche Diodes is evolving rapidly and has matured to the point at which it can address the requirements of a range of imaging applications. In this report we consider the current suitability and future potential of CMOS‐compatible Single Photon Avalanche Diodes to address the particular application of display metrology. [ABSTRACT FROM AUTHOR]

In this paper, an all-digital, 10-bit, low-power Time-to-Digital Converter (TDC) is proposed for use in biomedical applications. To reduce the area and power consumption, as well as provide noise shaping capability, the Gated Ring Oscillator (GRO) architecture is chosen as the core for the proposed TDC. Regarding the problems created by the leakage current in GROs, especially in low-frequency applications, a new approach for data capturing is used. The proposed modified data capturing method tackles the leakage current effect and allows the TDC to operate at ultralow frequencies. The proposed TDC achieves a dynamic range of 1.76 µs, and the resolution of 1.76 ns at 1KS/s sampling frequency. Simulations were performed using the 0.13 µm CMOS process. The TDC power consumption was 45.85 nW at a 0.4 V supply and the Signal to Noise and Distortion Ratio (SNDR) was 54.55 dB. [ABSTRACT FROM AUTHOR]

Purpose: A low power flip-flop circuit is designed for energy-efficient devices. Digital sequential circuits are in huge demand because every processor has most of the parts of digital circuit. The sequential circuits consist of a basic data storing element, a latch is used to store single bit data. The flip-flop takes a sufficient portion of the total chip area and overall power consumption as well. This study aims to the low power energy-efficient applications like laptops, mobile phones and palmtops. Design/methodology/approach: This paper proposes a new type of flip-flop that consists of the only 16 transistors with a single-phase clock. The flip-flop has two blocks, master and slave latch. In this design, the authors have focused on only master latch, which includes a level restoring circuit. It is used to help the master latch in data retention process. The latch circuit has two inverters in back-to-back arrangement. The proposed flip-flop is implemented on 65 nm complementary metal oxide semiconductor technology using Cadence Virtuoso environment and compared with other reported flip-flops. Findings: The proposed flip-flop architecture outperformed the peak percentage, i.e. 79.25% as compared to transmission gate flip-flop and a minimum of 20.02% compared to 18 T true single phase clocking (TSPC) improvement in terms of power. It also improved C to Q delay and power delay product. In addition, by reducing the number of transistors the total area of the proposed flip-flop is reduced by a minimum of 13.76% with respect to 18TSPC and existing flip-flop. For reliability checking the Monte Carlo simulation is performed for thousand samples and it is compared with the recently reported 18TSPC flip-flop. Originality/value: This work is tested by using a test circuit with a load capacitor of 0.2 fF. The proposed work uses a new topology to work as master-slave. Power consumption of this technique is very less and it is best suitable for low power applications. This circuit is working properly up to 2 GHz frequency. [ABSTRACT FROM AUTHOR]

Purpose: The primary aim of this paper is to present a novel design approach for a ring voltage-controlled oscillator (VCO) suitable for L-band applications, whose oscillation frequency is less sensitive to power supply variations. In a few decades, with the advancement of modern wireless communication equipment, there has been an increasing demand for low-power and robust communication systems for longer battery life. A sudden drop in power significantly affects the performance of the VCO. Supply insensitive circuit design is the backbone of uninterrupted VCO performance. Because of their important roles in a variety of applications, VCOs and phase locked loops (PLLs) have been the subject of significant research for decades. For a few decades, the VCO has been one of the major components used to provide a local frequency signal to the PLL. Design/methodology/approach: First, this paper chose to present recent developments on implemented techniques of ring VCO design for various applications. A complementary metal oxide semiconductor (CMOS)-based supply compensation technique is presented, which aims to reduce the change in oscillation frequency with the supply. The proposed circuit is designed and simulated on Cadence Virtuoso in 0.18 µm CMOS process under 1.8 V power supply. Active differential configuration with a cross-coupled NMOS structure is designed, which eliminates losses and negates supply noise. The proposed VCO is designed for excellent performance in many areas, including the L-band microwave frequency range, supply sensitivity, occupied area, power consumption and phase noise. Findings: This work provides the complete design aspect of a novel ring VCO design for the L-band frequency range, low phase noise, low occupied area and low power applications. The maximum value of the supply sensitivity for the proposed ring VCO is 1.31, which is achieved by changing the VDD by ±0.5%. A tuning frequency range of 1.47–1.81 GHz is achieved, which falls within the L-band frequency range. This frequency range is achieved by varying the control voltage from 0.0 to 0.8 V, which shows that the proposed ring VCO is also suitable for low voltage regions. The total power consumed by the proposed ring VCO is 14.70 mW, a remarkably low value using this large transistor count. The achievable value of phase noise is −88.76 dBc/Hz @ 1 MHz offset frequency, which is a relatively small value. The performance of the proposed ring VCO is also evaluated by the figure of merit, achieving −163.13 dBc/Hz, which assures the specificity of the proposed design. The process and temperature variation simulations also validate the proposed design. The proposed oscillator occupied an extremely small area of only 0.00019 mm2 compared to contemporary designs. Originality/value: The proposed CMOS-based supply compensation method is a unique design with the size and other parameters of the components used. All the data and results obtained show its originality in comparison with other designs. The obtained results are preserved to the fullest extent. [ABSTRACT FROM AUTHOR]

Severe conditions such as high-energy particle strikes may induce soft errors in on-chip memory, like cache and translation lookaside buffers (TLBs). As the key component of virtual-to-physical address translation, TLB directly affects processor performance. To protect the virtual page information stored in TLB, several studies have introduced error detection or correction codes. However, most schemes proposed for data TLB cannot support the detection of multi-bit upsets, which is reported as a serious issue in modern fault-tolerant processors due to the downscaling of CMOS process technology. In this paper, we propose a new two-dimensional protection technique, called the matrix protection tag (MaP-Tag), to provide stronger error detection and correction capability to TLB virtual page information. Our proposal reorganizes virtual page information into a matrix and employs adjacent check bits and interleaved check bits for error detection. The two-dimensional design offers one-bit error detection, burst multi-bit error detection, and even multi-bit error correction in some cases. The simulation results show that our proposal can detect almost all error patterns when injected with up to eight bit-flips. Furthermore, the technique provides a better error correction rate than conventional single error correction (SEC) codes. The reliability calculation shows that our proposal is powerful in both error detection and correction with affordable storage overhead. [ABSTRACT FROM AUTHOR]

This paper presents a novel adaptive reconfigurable rectifier architecture for radio frequency energy harvesting (RFEH); in addition, a new metric for high-efficiency dynamic range (DR) is proposed. The presented rectifier architecture is based on a double-sided diode-feedback cross-coupled differential-drive rectifier (CCDR) structure incorporating self-body bias for reconfigurable operation. An adaptive structure based on a Schmitt trigger is proposed to adaptively switch the rectifier connection without auxiliary voltage (Vaux), with two rectifier stages in parallel at low power and in series at high power. The system is simulated at a 180 nm CMOS process and the results show more than 17 dB DR at 900 MHz, with efficiency higher than 50% at a 100 kΩ load. [ABSTRACT FROM AUTHOR]

The work reported in this paper describes the design and simulation of a novel current mirror readout circuit based MOSFET integrated cantilever structure for micro-gram (μ g) mass sensing applications. The proposed mass sensing structure consist of silicon cantilever as the micromechanical structure, MOSFET as strain sensing element and current mirror as a readout circuit. In this paper, studies have been carried out on three structures (a) n-channel MOSFET based resistive loaded current mirror integrated cantilever mass sensor (b) p-channel MOSFET based resistive loaded current mirror integrated cantilever mass sensor and (c) n- and p- channel MOSFETs based dual current mirror integrated cantilever mass sensor. The input MOSFET(s) of the current mirror acts as the reference transistor(s) while the output MOSFET(s) of the mirror circuit acts as strain sensing element(s) to measure the cantilever deflection under externally applied load. The structural and the electrical characteristics of the sensors were simulated using COMSOL Multiphysics and TSPICE software respectively. Simulation results showed a sensitivity of 21.89 μ V/ μ g, 1 μ V/ μ g and 115.57 μ V/ μ g for nMOS, pMOS and dual channel cantilever mass sensor. The fabrication steps and mask layout of the proposed sensor have also been presented in this paper. The novelty of this work is emphasized by the innovative integration of a CMOS current mirror circuit with a cantilever for mass sensing. [ABSTRACT FROM AUTHOR]

This paper introduces an innovative two-stage distributed RC oscillator design, enhancing the noise performance and frequency stability for compact electronic devices. This work significantly reduces the comparator noise and improves system reliability by implementing a novel approach to increase the signal transition slope, coupled with optimized resistor and capacitor configurations. The study employs a quadrature oscillator topology and a precise reference voltage generation method, effectively addressing the challenges of mismatch and noise performance. A 469.2 kHz quadrature oscillator with two-stage distributed RC is implemented with a 0.18 μm CMOS process, achieving a FoM of −160 dBc/Hz at 100 Hz with a stable −20 dB roll-off in the phase noise and an Allan deviation floor of less than 0.7 ppm. [ABSTRACT FROM AUTHOR]

The reduction in size of metal oxide semiconductor (MOS) devices results in the increase of leakage current due to Quantum effects. The different technologies proposed to overcome this problem. Variant structures of MOSFET such as Tri Gate FinFET or Pi gate and Omega gate to enhance current drive and control over the Short Channel Effects (SCE). In advanced technology node, the performance of CMOS circuits degrades. In sub 10 nm nodes technologies, FinFETs have a good channel control with high ON current (ION).Nowadays, power dissipation and leakage current are one the two crucial issues that the modern electronic industry is facing in 3 nm node technology. The other alternative devices such as novel GAA (Gate All Around) FinFET have been proposed to address these problems. This structure gained huge attention because of their possible fabrication process.In this paper, for the first time, we have investigated and simulated the different electrical characteristics of GAA FinFET 3 nm with N channel using HfO2 (high k material oxide) to improve the subthreshold characteristics. In the second part of this paper, we present a novel correction for the equations used in this technology because no n-well layer is required anymore as the device channel is totally surrounded by the gate which enables the placement of n and p devices in a CMOS gate much closer to each other than previous technologies. [ABSTRACT FROM AUTHOR]

In this paper, a monopole patch antenna is designed, and the structure of the antenna is analyzed. The manufacturing process adopts TSMC 0.18 μm CMOS process technology. An artificial magnetic conductor (AMC) on the M1 layer is proposed in this paper to increase the radiation gain and reduce the reflection coefficient (S11) magnitude for impedance matching and antenna performance. This method can make up for the radiation efficiency and benefits of the antenna-on-chip that are affected by the high dielectric constant and low resistivity of the silicon substrate of the CMOS process. The antenna designed in this paper obtains a simulated bandwidth of 37.5 GHz to 69.5 GHz using the Electromagnetic Simulation Software, and the fractional bandwidth of the design is 60%. Among them, 62 GHz shows a maximum gain value of −2.64 dBi. Actual measurements have confirmed that the reflection coefficient of the antenna on the chip proposed in this paper is the same as the simulation trend, and a wider bandwidth is obtained from 20.9 GHz to 67 GHz, with a fractional bandwidth of 104.89%. This bandwidth covers millimeter wave 28 GHz, 38 GHz, and 60 GHz application frequencies. [ABSTRACT FROM AUTHOR]