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In this paper, a CMOS antiphase power amplifier (PA) is presented with a multigate transistor (MGTR) technique that improves its linearity. The drive stage of the PA is biased in the subthreshold region, such as in class C, to realize the antiphase technique. The nonlinearity of the power stage of the PA is canceled out using the third-order intermodulation distortion and phase distortion of the drive stage. The cancellation effect is further optimized and enhanced without any performance degradation with the aid of the proposed MGTR technique at the drive stage. Unlike the traditional technique, which suppresses the nonlinearity of the PA, the MGTR technique is used to enhance the nonlinearity of the drive stage to cancel out the significant nonlinearity of the power stage. The proposed PA is fabricated with a 180-nm RF CMOS process and used to verify the linearity by WCDMA and LTE signals. The measurement results show an average output power of 25.8 dBm, PAE of 28%, and error vector magnitude of 3% at 1.85 GHz for the WCDMA. The PA also shows an average output power of 24.4–25.8 dBm at 1.7–2.0 GHz for the WCDMA. The PA is verified for LTE signals with 10 MHz of bandwidth/16 QAM and with 20 MHz of bandwidth/64 QAM. No digital predistortion or off-chip components are utilized. [ABSTRACT FROM PUBLISHER]

ABSTRACT In this study, we design an X-band switching-mode CMOS power amplifier using 0.13-μm RF CMOS process. The power amplifier is composed of driver and power stages. In this study, we focus on the power consumption of the driver stage. To minimize power consumption, we propose a shot-through current rejection technique for the Class-D amplifier used as a driver stage of the CMOS power amplifier. We split the gate bias of the NMOS and PMOS of the Class-D amplifier using DC-blocking capacitors to control the shot-through current. From the measured results, we successfully prove the feasibility of the proposed technique. © 2014 Wiley Periodicals, Inc. Microwave Opt Technol Lett 56:1159-1162, 2014 [ABSTRACT FROM AUTHOR]

ABSTRACT In this work, we analyzed the efficiency of a switching-mode RF CMOS power amplifier with the following design parameters: the on resistance and the parasitic capacitance of the power transistor. The power amplifier is composed of a class-D type driver stage and a class-E type power stage. The power consumption of the driver stage, the load impedance of the power stage, and the loss of the output matching networks are considered for a numerical analysis. We investigated the normalized drain efficiency according to the variable supply voltage of the power stage for polar transmitter applications. From the simulated results of the power amplifier, we successfully proved the feasibility of using the numerical analysis. The designed power amplifier is implemented using 0.13 μm RF CMOS process to verify the numerical results by means of an experiment. A distributed active transformer is used for an output matching network. © 2014 Wiley Periodicals, Inc. Microwave Opt Technol Lett 56:110-117, 2014 [ABSTRACT FROM AUTHOR]

Abstract: A wireless type of chip-to-chip communication (WCC) technology is proposed as the next generation of 3D semiconductor technology. To demonstrate the feasibility of this technology, we designed a coil, transmitter and receiver for wireless chip-to-chip communication using a 50-nm digital CMOS process. The coil is designed using inductive coupling with design parameters that include the number of turns, the metal width, and the space between adjacent metal lines. A differential transceiver structure is proposed for the WCC technology. The transmitter of the transceiver acts as a termination and bias circuit for the receiver while the transceiver is operating as a receiver. The receiver is designed with a typical differential amplifier and a latch to recover the transmitted original digital signal. The proposed transceiver and coil for the proposed WCC technology is implemented using commercial 50-nm digital CMOS technology. Experimental results successfully demonstrate the feasibility of the WCC technology. [Copyright &y& Elsevier]

In this work, we analyze the effects of an inter-stage capacitor located between the power stage input and the driver stage output on the overall efficiency of a RF CMOS power amplifier and on gate-drain reliability problems. To verify the analyzed effects, we designed a RF CMOS power amplifier with a center frequency of 1.85-GHz. Class-D amplifiers with a feedback resistor are used as driver stages, and a class-E amplifier is used as the power stage. A distributed active transformer is adapted for use in the output power combiner for high efficiency. The inter-stage capacitor between driver and the power stage is removed to enhance the switching operation of the power stage. By eliminating the inter-stage capacitor, the supply voltage of the driver stage can be decreased compared to that in a general amplifier. Accordingly, the power-added efficiency is improved and the gate-drain reliability problems are moderated compared to a general amplifier. The analyzed effect of the inter-stage capacitor is verified successfully using the measured results of the designed amplifiers. [ABSTRACT FROM AUTHOR]