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This paper presents a 14 bit 35 MS/s successive approximation register (SAR) ADC that achieves a nearly constant 74.5 dB peak SNDR up to Nyquist and an SFDR of 90/99 dB for inputs near Nyquist and at low-frequencies, respectively. The ADC employs a loop-embedded input buffer that shields the large sampling capacitor from the input and thereby eases the ADC drive requirements significantly. Since the buffer's nonlinearity is cancelled by the SAR operation, a pair of basic source followers can be used, adding only 12.5 mW (23% of the total power) to the power budget. The ADC includes a bandgap reference and a self-calibrated current steering DAC to close the SAR loop, which eliminates the need for a low-impedance off-chip reference. The design occupies 0.236 mm^2 in 40 nm CMOS and consumes a total power of 54.5 mW from its 1.2/2.5 V supplies, leading to an SNDR-based Schreier FOM of 159.5 dB at Nyquist. [ABSTRACT FROM PUBLISHER]

A low-power pipelined ADC featuring dynamic source follower amplifiers is presented in this paper. The proposed dynamic source follower-based architecture provides a low-power alternative to the traditional opamp-based MDAC circuits. This new type of circuit dynamically charges its load capacitance without a large bias current, leading to significant power savings. The presented ADC includes a low-power comparator with offset calibration and uses digital calibration for gain correction. Measured results indicate that the 9.4-bit, SO-MS/s prototype ADC achieves an SNDR of 49.2 dB (7.9 ENOB) and consumes 1.44 mW from a 1.2-V supply, resulting in a figure of merit of 119 fJ/conversion-step. The converter's input capacitance is 90 fF and the total active area is 0.123 mm[sup2] in a 90 nm CMOS process. [ABSTRACT FROM AUTHOR]

The residue amplifiers in high-speed pipelined analog-to-digital converters (ADCs) typically determine the converter's overall speed and power performance. We propose a mixed-signal technique that exploits incomplete settling to achieve low power residue amplification. In the first stage of a 12-bit, 75-MS/s proof-of-concept prototype, the employed open-loop residue amplifier dissipates only 2.9 mW from a 3-V supply, achieving >60% amplifier power reduction over a previously reported open-loop residue amplifier implementation and achieving >90% amplifier power reduction over a conventional opamp implementation. Test results show that the converter's maximum signal-to-noise-and-distortion ratio (SNDR) is 65.6 dB. The measured integral and differential nonlinearity are 0.95 LSB and 0.64 LSB, respectively. The experimental chip occupies 7.9 mm² and consumes 273 mW in a 0.35-μm double-poly, quadruple-metal CMOS process. [ABSTRACT FROM AUTHOR]

Electrostatic discharge (ESD) protection circuits typically contain a significant amount of nonlinear capacitance. At high frequencies and large amplitudes, this nonlinearity can degrade the signal integrity at the input pins of high performance mixed signal ICs, such as analog-to-digital converters (ADCs). This study provides a theoretical analysis of this problem as well as experimental results that quantify typical distortion levels introduced by state-of-the-art ESD structures, It is shown that with distortion targets nearing — 100 dBc at signal frequencies on the order of 100 MHz, ESD circuits, will become a limiting factor in the future. In addition to these results, this study offers some brief guidelines for designing ESD protection circuits suitable for high-speed, high-linearity applications. [ABSTRACT FROM AUTHOR]

This paper explores modeling and technology-scaling issues related to analog performance in advanced CMOS technologies. Performance metrics for analog circuits are defined, to provide insight into the impact of device scaling on power-constrained analog circuit design. Current and previous generation technologies (90 nm and older) are evaluated using standard compact models. Technology nodes below 90 nm are simulated at the device level to show trends in analog performance metrics and to evaluate the impact of nonminimum gate length and alternate doping profiles. Results indicate that the modeling of moderate-to-weak inversion behavior will continue to grow in importance. Simulations suggest that using nonminimum length and drain-side engineered devices at the 45-nm technology node offers an attractive degree of freedom for analog circuit design. [ABSTRACT FROM AUTHOR]

Precision amplifiers dominate the power dissipation in most high-speed pipelined analog-to-digital converters (ADCs). We propose a digital background calibration technique as an enabling element to replace precision amplifiers by simple power efficient open-loop stages. In the multibit first stage of a 12-bit 75-MSamples/s proof-of-concept prototype, we achieve more than 60% residue amplifier power savings over a conventional implementation. The ADC has been fabricated in a 0.35-µm double-poly quadruple-metal CMOS technology and achieves typical differential and integral nonlinearity within 0.5 LSB and 0.9 LSB, respectively. At Nyquist input frequencies, the measured signal-to-noise ratio is 67 dB and the total harmonic distortion is -74 dB. The IC consumes 290 mW at 3 V and occupies 7.9 mm². [ABSTRACT FROM AUTHOR]