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A new two-element phase-locked loop (PLL)-coupled array for the implementation of millimeter-wave (mm-wave) and subterahertz (sub-THz) phased arrays is presented. This architecture avoids using lossy phase shifter to create the required phase shift between the adjacent elements in a phased-array system. The required phase shift is generated by utilizing a dual nested loop PLL. The two PLL loops work together to stabilize the frequency and create the required phase shift. Moreover, it can be scaled simply by adding more unit cells to the architecture. A 112–121-GHz two-element phased array is designed and fabricated in a standard 65-nm CMOS process. It consumes 147-mW power and provides a phase shift of 46.7° ranging from 58.53° to 105.2° at 117 GHz. [ABSTRACT FROM AUTHOR]

After completing two years as Editors-in-Chief of this Transactions, it is a good time to say a few words on how this journal is accomplishing its mission of serving the microwave community. [ABSTRACT FROM AUTHOR]

Based on time-variant behavior of metal-oxide–semiconductor field-effect transistors in large-signal operations, harmonic translations and their mutual effects are analyzed. Large amplitudes at terminal voltages of these transistors push them into different regions of operation. In this paper, harmonic translations are derived as a result of such changes in operation region of transistors. Operation in triode region for a portion of oscillation cycle results in iterative harmonic translations between fundamental frequency and second harmonic. They boost each other constructively for significantly stronger oscillation, more second harmonic output power, and enhanced dc-to-RF efficiency. Based on this analysis, a 215-GHz signal source, implemented in a TSMC 65-nm CMOS LP is presented. The proposed oscillator achieves a maximum output power of 5.6 dBm and a dc-to-RF efficiency of 4.6%. The measured phase noise is −94.6 dBc/Hz at 1-MHz offset. The proposed oscillator occupies only 0.08 mm2 of chip area. [ABSTRACT FROM PUBLISHER]

A voltage controlled oscillator (VCO) incorporating a system of coupled oscillators with two active mode switching (AMS) blocks is presented. The AMS blocks excite the main VCOs to operate in two distinct frequency bands. An overlap between the two frequency bands has extended the tuning range of the VCO. By turning the AMS blocks off, low-loss and low-capacitance behaviors of these blocks result in wide tuning range and high harmonic output power at high millimeter-wave frequencies. On the other hand, by turning the AMS blocks on, their loss-canceling and capacitance-tuning behaviors yield to higher power and wider tuning range with a lower center frequency. By having sufficient frequency overlap between the two modes, the implemented VCO achieves record tuning range of 20.7% at 190.5 GHz with a maximum output power of –2.1 dBm. This tuning range is significantly higher than reported silicon-based VCOs with center frequencies higher than 120 GHz. [ABSTRACT FROM PUBLISHER]

A 300 GHz frequency synthesizer incorporating a triple-push VCO with Colpitts-based active varactor (CAV) and a divider with three-phase injection is introduced. The CAV provides frequency tunability, enhances harmonic power, and buffers/injects the VCO fundamental signal from/to the divider. The locking range of the divider is vastly improved due to the fact that the three-phase injection introduces larger allowable phase change and injection power into the divider loop. Implemented in 90 nm SiGe BiCMOS, the synthesizer achieves a phase-noise of –77.8 dBc/Hz (–82.5 dBc/Hz) at 100 kHz (1 MHz) offset with a crystal reference, and an overall locking range of 280.32–303.36 GHz (7.9%). [ABSTRACT FROM AUTHOR]

We introduce a novel frequency tuning method for high-power terahertz sources in CMOS. In this technique, multiple core oscillators are coupled to generate, combine, and deliver their harmonic power to the output node without using varactors. By exploiting the theory of nonlinear dynamics, we control the coupling between the cores to set their phase shift and frequency. Using this method, two high-power terahertz VCOs are fabricated in a 65 nm LP bulk CMOS process. The first one has a measured output power of 0.76 mW at 290 GHz with 4.5% tuning range and the output power of the second VCO is 0.46 mW at 320 GHz with 2.6% tuning range. The output power of these signal sources is 4 orders of magnitude higher than previous CMOS VCOs and is even higher than VCOs implemented in compound semiconductors with much higher cut-off frequencies. [ABSTRACT FROM AUTHOR]

In this paper, we study an electrical nonlinear medium consisting of voltage-dependent capacitors and inductors to generate sharp pulses from a lower frequency sinusoid. First, we analyze the optimum conditions for maximum harmonic generation in a uniform nonlinear line. Next, we extend the nonlinear line to a two-dimensional nonlinear lattice that is compatible with CMOS technology. Compared with the nonlinear line, the lattice relies on spatial power combining, higher cut-off frequency, and nonlinear wave interaction to enhance the pulse amplitude and sharpness. To show the feasibility of this method, we implement the first CMOS nonlinear lattice in a 0.13-\mum CMOS process, and successfully demonstrate 2.7-Vpp, 6.3-ps pulses from a 22-GHz input signal. [ABSTRACT FROM AUTHOR]

A wideband frequency multiplier that effectively generates and combines the even harmonics from multiple transistors is proposed. It takes advantage of standing-wave formation and loss cancellation in a distributed structure to generate high amplitude signals resulting in high harmonic power. Wide bandwidth operation and odd harmonic cancellation around the center frequency are the inherent properties of this frequency multiplier. Using this methodology, we implemented a frequency doubler that operates from 220 GHz to 275 GHz in a standard 65 nm CMOS process. Output power of -6.6 dBm (0.22 mW) and conversion loss of 11.4 dB are measured at 244 GHz. [ABSTRACT FROM AUTHOR]

A systematic approach to designing high frequency and high power oscillators using activity condition is introduced. This method finds the best topology to achieve frequencies close to the f\max of the transistors. It also determines the maximum frequency of oscillation for a fixed circuit topology, considering the quality factor of the passive components. Using this technique, in a 0.13 \mum CMOS process, we design and implement 121 GHz and 104 GHz fundamental oscillators with the output power of -3.5 dBm and -2.7 dBm, respectively. Next, we introduce a novel triple-push structure to realize 256 GHz and 482 GHz oscillators. The 256 GHz oscillator was implemented in a 0.13 \mum CMOS process and the output power of -17 dBm was measured. The 482 GHz oscillator generates -7.9 dBm (0.16 mW) in a 65 nm CMOS process. [ABSTRACT FROM PUBLISHER]

A 2-D electrical filter is introduced that is compatible with today's conventional integrated circuit processes. The rich 2-D propagation properties of the medium are used to introduce a novel high quality factor filter called an electrical prism. The pro- posed filter shows a quality factor much larger than the quality factor of the individual components at high millimeter-wave and terahertz frequencies. This structure also provides a negative effective index in a low-pass LC lattice. Based on this idea, we show filters with quality factors of 130 at 230 GHz and 420 at 460 GHz consisting of elements with the quality factor of 10 and 20, respectively. The effect of component loss on the filter quality factor is discussed in this paper. The negative effective index and the filter behavior of the lattice is verified by measuring a prototype on a CMOS process at 32-40 GHz. There is good agreement among the theory, simulation, and experimental results. [ABSTRACT FROM AUTHOR]