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An 802.11n-draft-compliant 2 × 2, 2-stream MIMO radio SoC, incorporating two dual-band RF transceivers, analog baseband filters, data converters, digital PHY and MAC, and a PCI Express interface, has been integrated in a standard 0.13- μm digital CMOS technology with a die area of 36 mm2 . The receiver achieves noise figures of 4 dB and 6 dB, respectively, at 2.4 GHz and 5 GHz. The transmitter EVM for a 2-stream, 40-MHz-bandwidth 64-QAM OFDM signal is - 31 dBc at 2.4 GHz and - 8 dBm output power and - 31.5 dBc at 5 GHz and - 4 dBm output power. [ABSTRACT FROM AUTHOR]

A single-chip lEEE-802.11g-compliant wireless LAN system-on-a-chip (SoC) that implements all RF, analog, digital PHY and MAC functions has been integrated in a 0.18-µm CMOS technology. The IC transmits 0-dBm EVM-compliant output power for a 64-QAM OFDM signal. The overall receiver sensitivities are better than -92 and -73 dBm for data rates of 6 and 54 Mb/s, respectively. [ABSTRACT FROM AUTHOR]

A single-chip dual-band tri-mode CMOS transceiver that implements the RF and analog front-end for an IEEE 802.11a/b/g wireless LAN is described. The chip is implemented in a 0.25-μm CMOS technology and occupies a total silicon area of 23 mm2. The IC transmits 9 dBm/8 dBm error vector magnitude (EVM)-compliant output power for a 64-QAM OFDM signal. The overall receiver noise figure is 5.5/4.5 dB at 5 GHz/2.4 GHz. The phase noise is -105 dBc/Hz at a 10-kHz offset and the spurs are below -64 dBc when measured at the 5-GHz transmitter output. [ABSTRACT FROM AUTHOR]

Discusses the integration of a transceiver comprising the radio frequency and analog circuits of a wireless local area network in a complementary metal oxide semiconductor technology. Maximum transmitted power; Overall receive-chain noise figure; Measurement of the synthesizer phase noise.