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The resolution of time-to-digital converters (TDC) is one parameter that will define its efficiency. This research demonstrates a 5.4 ps TDC with anti-PVT-variation implemented in 90-nm CMOS technology. The proposed converter uses a two-step architecture. The first stage is a Buffer Delay Line (BDL) to acquire a wide dynamic range characteristic. The second stage that will provide a higher resolution is Vernier delay line which receives the start and stop signals from the edge detector. A PVT (process, voltage, temperature) corner detector is equipped in the proposed TDC to resist the PVT variation. The proposed TDC's post-layout simulation results achieve a delay variation of 2 ps and a resolution of 5.4 ps, and an acceptable dynamic range of 890 ps. The INL and DNL attained a value of 0.8 and −1 LSB from the simulations. The proposed TDC attains the best FOM based on post-layout simulations with a value of 0.177, which makes it superior to all prior designs. [ABSTRACT FROM AUTHOR]

This paper describes an efficient method of designing and implementing in FPGA devices complex tapped delay lines (CTDL) with pico and sub-picosecond resolution. Achieving a higher resolution and better linearity is possible by appropriate selection of single time coding tapped delay lines (TDL) involved in creation of CDTL. The proposed TDL selection algorithm significantly optimizes the size of the device's logical resources required to implement CDTL with assumed parameters and provides a proper selection scenario. Ultimately, the presented solution allows to create CTDLs with different user-defined configurations based on a fixed set of available logical resources. Therefore, it is particularly recommended for prototyping in smaller FPGA devices. In this work, we investigate how the order of line selection influences the increase of the multiple time coding lines resolution. Furthermore, we determine the relation between the equivalent resolution value and the number of TDLs involved. Obtained results allow to estimate the upper limit of resolution that can be achieved using a given technology. In addition, the ranges of resolutions achievable with a fixed number of lines is also examined. The presented research results have been performed on a Kintex UltraScale FPGA chip, manufactured by Xilinx in the 20-nm CMOS process. [ABSTRACT FROM AUTHOR]

This study introduces an all-digital CMOS time-domain smart temperature sensor (STS) that offers a smaller circuit area and reduced complexity. In contrast to previous studies that utilized multiple delay lines or additional path selection circuits, the proposed new structure employs a single cyclic path and fewer delay lines. The functionality of high-resolution temperature sensing, pulse-shrinking time measurement, and built-in offset-error cancellation is achieved using only one cyclic delay line (CDL). The temperature-sensing delay line generates a thermal-dependent pulse width proportional to the absolute temperature (PTAT). Subsequently, a pulse-shrinking unit, implemented within the pulse-shrinking delay line, performs time-to-digital conversion by measuring the PTAT pulse width. Finally, a time-added delay line within the CDL incorporates a simple D-type Flip Flop to enable concise offset-error cancellation, thereby improving accuracy. This study further simplifies the cancellation circuitry to reduce the overall circuit area. The proposed sensor, fabricated using a TSMC 0.35 μ m CMOS process, occupies an area of 0.022 mm 2 , providing a cost-effective solution for pulse-shrinking STSs. The maximum inaccuracy after offset-error cancellation is 1. 3 ∘ C within a temperature range of 0 ∼ 80 ∘ C, with a high resolution of approximately 0. 035 ∘ C/LSB. This resolution enhancement significantly surpasses similar studies. By reducing circuit complexity, the proposed sensor successfully achieves improvements in both area and resolution. [ABSTRACT FROM AUTHOR]

This paper proposes wide-range and fast locking all-digital delay-locked loop (WRADDLL) circuit with one cycle dynamic synchronizing. The WRADDLL not only synchronizes the input and output clocks in 5 clock cycles but maintains one cycle dynamic locking. The WRADDLL reduces the clock skew between the input and output clocks with three innovative techniques. First, by improving the mirror control circuit, the WRADDLL operates correctly with a flexible duty cycle clock signal. Second, the WRADDLL works precisely and ignores the effect of output load changes by moving the measurement delay line beyond the output driver. Besides, it can achieve one-cycle dynamic locking. Finally, the WRADDLL utilizes the band selector to achieve wide-range operation. After fine tuning, the maximum static phase error is less than 3% of clock cycle. The chip is fabricated by 90 nm standard CMOS process. Its operating frequency range is from 200 MHz to 2 GHz. The power consumption and RMS jitter are 3.24 mW and 1.49 ps at 2 GHz, respectively. The active area of this chip is 0.011 mm2. [ABSTRACT FROM AUTHOR]

Analog–digital converters (ADCs) are electronic circuits that convert continuous time signals into digital signals (binary data) for analyzing, estimation, and transmission. Transceivers use ADC in the baseband stage of receiver to convert the analog signals to digital form for further signal processing. At high-frequency applications, like millimeter wave applications, the ADC consumes more power due to the high sampling rate with respect to the increased bandwidth. In this article, a novel dynamic comparator is presented with delay and power analysis for the design. The expression is derived for all operational regions of the transistor. The new design is proposed for low-power consumption and reduced delay of the circuit. The novel design overcomes the drawbacks of the less operating frequency range, high latency, and more power dissipation of existing comparator designs. The proposed low-power dynamic comparator is simulated with 45 nm CMOS technology that provides total power dissipation of 33.92 µW, delay of 19.71 ps, and energy per conversion of 0.19 fJ/conv. with a supply voltage of 1 V. [ABSTRACT FROM AUTHOR]

A high image rejection 38 GHz demodulator in TSMC 65-nm CMOS process is presented. To achieve better than −40 dBc image rejection ratio (IRR), a low I/Q mismatch 45° LO power splitter of sub-harmonic mixer is proposed. In this design, the 45° LO power splitter is composed of a Wilkinson divider, a series delay line with electrical length of 45° on one side of the divider, and a shunt 90° transmission line on the other side. This configuration is attractive because of its design simplicity and easy fabrication. Compared with the conventional techniques that utilize capacitors and inductors instead of the shunt 90° transmission line, the proposed LO power splitter can alleviate the issue of process variation. The demodulator demonstrates an IRR lower than −40 dBc from 37.5 to 41.5 GHz. In addition, conversion gain is 1.3 ± 0.9 dB from 33 to 41 GHz with 6 dBm LO power. The total direct current power consumption is 78 mW from 1.0 V supply voltage. At the modulation scheme of 4096-QAM, the proposed demodulator demonstrates 1.7% (−35.1 dB) error vector magnitude (EVM), which is very close to the EVM measurement floor 1.6% (−36 dB) of our millimeter-wave signal analyzer. [ABSTRACT FROM AUTHOR]

A three-step tapered bit period asynchronous successive approximation register (SAR) analog-to-digital converter (ADC) is proposed to reduce the total DAC settling time by 47.7% compared to the non-tapered conversion time with less design overhead. Unlike conventional approaches, the SAR settling time analysis with both reference buffer output impedance and hardware overhead is first analyzed in each conversion step, which demonstrates that the three-step tapered bit period approach is the most time- and hardware efficient in our design. Additionally, area-efficient three-step clock generation is proposed by sharing resistors for delay generation, resulting in a small area increase of only 20.4% compared to the non-tapered clock generation. As a result, the proposed technique is used to reduce the reference buffer's power and increase the sampling frequency. The maximum allowed output impedance of the reference buffer for SFDR > 92 dB becomes larger than that of the non-tapered design by 200 Ω , translated to a sampling frequency increase from 6 MHz to 8 MHz in our design. The proposed three-step tapered bit period using an area-efficient clock generator was designed in a 55 nm CMOS process. The clock generator occupies 0.00081 mm 2 out of 1143 μ m × 81 μ m overall size. The power consumption of the 8 MS/s 12-bit SAR ADC with proposed clock generation is 128.91 μ W when under 1 V supply. [ABSTRACT FROM AUTHOR]

This paper presents a fast lock-in time clock frequency multiplier without using traditional clock generation circuits such as PLLs and DLLs. We propose a novel technique based on capacitive finite impulse response (FIR) filters to generate clock phases while reducing the input clock phase noise at the same time. A new delay line circuit is also proposed for improving power supply rejection. In addition, to improve the matching quality as well as the end-effects tolerance of the on-chip capacitors, a single-value series/parallel algorithm is proposed. Designed in a 0.18 μ m digital CMOS process, with a 20 MHz input clock frequency, the multiplier achieves a multiplication factor of 5 with a lock-in time of less than 4 clock cycles. The input clock jitter is reduced from 7ns RMS to 153 ps RMS after frequency multiplication. [ABSTRACT FROM AUTHOR]

This paper presents a delay-locked loop (DLL) with multiple radiation-hardened techniques. A radiation-hardened charge pump (RH-CP) and a radiation-hardened voltage-controlled delay line (RH-VCDL) are proposed to mitigate effects on DLLs caused by single-event transient (SET). A lock detection module (LDM) is designed in the RH-CP to separate CP and VCDL when the DLL is locked. Thanks to LDM, the voltage transients caused by ion strikes on CP can be prevented from effecting the control voltage of VCDL and causing inverted lock error. A SET correction module (SCM) combined with sliced delay cells is used in the RH-VCDL to select the uncorrupted output and avoid missing pulses errors occurring at the output of DLL. The proposed DLL is designed in 22-nm CMOS process with an operation frequency of 5 GHz. Simulations at linear energy transfer (LET) between 40 and 100 MeV-cm2/mg show that RH-CP eliminates inverted lock error and RH-VCDL mitigates missing pulses generated by the DLL after ion strikes effectively. [ABSTRACT FROM AUTHOR]

In the present era, FET devices are seamlessly integrated with complex circuits that can be used to realize chips capable of operating at a significantly higher speed. These designed devices can meet the requisite of circuits used in designing mobile phones, tablets and laptops, thereby enhancing the overall performance. The present work focuses on designing of gate stack inverted-T junctionless FET at 20 nm technology node. Both static and low frequency characteristics of device such as threshold voltage (V T h ), transconductance (g m), on (I O N ) & off (I O F F ) state currents, as well as its high-frequency characteristics like total gate capacitance (C g g ), cut-off frequency (f T), maximum oscillation frequency (f max) and gain bandwidth product (GBW) are methodically demonstrated with alterations in the device process and geometrical variations. The parameters such as height of fin, width of fin and work function are varied to study their impact. The SS, DIBL, I O N / I O F F (current switching ratio) and V T h , for 20 nm gate length are observed as 67.94 mV/dec, 34.32 mV/V, 108, 0.32 V, respectively. The f max is determined to be in the THz range and has early voltage of approximately 6.12V. Additionally, the effect of temperature is also studied by varying it in the range of 250 K–450 K. Analysis and virtual modelling of device is carried out using Visual TCAD. In addition, p-channel transistor is designed along with the n-channel configuration to investigate the device performance for CMOS based circuits. The noise margin and average delay of the inverter circuit are observed to be 0.37 V and 36.7 ps respectively. • Analog and RF performance of the Gate-stack inverted-T junctionless FET is studied by varying the geometrical and process parameters. • In addition to that, impact of temperature variations is studied by varying them in the range of 250K–450K. • Taller fins are preferred to achieve higher on-state current and thinner fins are desired for improved short channel effects. • Increasing the metal gate work function increases the threshold voltage, whereas it reduces the off-state current with minimal effect on the on-state current. • The maximum operating frequency of the proposed device is 8.11 THz, and it has an early voltage of 6.32 V. [ABSTRACT FROM AUTHOR]

This paper proposes a digital delay locked loop (DLL) with a monotonic delay line (DL). This DLL adopts the calibration mode to reduce the non‐monotonic effects for the coarse‐tuning delay line (CTDL) and the fine‐tuning delay line (FTDL). The calibration mode detects the delay time of the delay unit, the timing resolution of CTDL, to adjust the delay range of the FTDL. Thus, the calibration mode can limit the overlap range of the delay time between the CTDL and the FTDL. The proposed DLL was implemented using a 0.18‐μm CMOS process, and the RMS and the peak‐to‐peak jitters of the DLL were 0.21% and 1.72%, respectively, at 560 MHz. [ABSTRACT FROM AUTHOR]

A three bit digitally controlled differential delay circuit is investigated in this work. The circuit is coupled to a normal high current power delivery network (PDN), which is capable of coming up from sleep mode (0 A) to 10 or 30 A or else 50 A in 10 ns. Simulated in a 0.09- μ m CMOS process and power supply voltage ( V dd ) of 1.1 V, the proposed circuit in post-layout can operate from 435.5 ps to 152.2 ps. The corresponding input vector (CBA) during this period switches from 000 to 111. Further, there are also intermediate states as the delay varies between the said ranges. These values of delay being dependent on the input vector has been noted to reduce monotonically. In addition to that, the post-layout delay sustains a shift of 4.0 and 6.5 ps for NN and SS process corner, respectively, following a ± 1 0 ∘ C change in temperature. But an abrupt high current I (t) pumped into the chip causes the voltage ( V p ) near the device to drop due to PDN. It also fluctuates with the natural frequency of PDN. The noise so developed induces jitter in the output swing and causes more delay between input and output in comparison to the circuit designed with zero noise in power supply. The jitter achieved for a current ramp I (t) of 0–50 A in 10 ns for the two vector CBA happens to be around 5.0 and 4.4 ps, respectively. The current ramp also generates power supply noise of 0.468 V occurring close to the silicon chip. This, in turn, corresponds to a V p of 0.642 V near the die, appearing to be much less than the required V dd of 1.1 V. Therefore, the delay is found to be affected significantly due to the sudden current ramp. It is also noted that a constant DC voltage of 0.642 V has quite different effect on delay and jitter than a fluctuating AC noise having the first droop same as that DC voltage. [ABSTRACT FROM AUTHOR]

This article presents a commutated-inductor–capacitor (commutated- $LC$) or switched- $LC$ circuit that acts as a radio frequency (RF) delay line. Thanks to its linear-periodically time-varying (LPTV) operation and fully passive implementation, it concurrently achieves long maximum delays, fine delay tuning steps, and wide instantaneous bandwidths while being low loss and highly linear. Unlike existing LPTV switched-capacitor broadband delays, the introduction of inductors in the proposed commutated- $LC$ delay circuit provides a new degree of freedom, allowing it to operate at a much higher RF with a wider instantaneous bandwidth. A proof-of-concept prototype in a 65-nm CMOS process demonstrates a measured 1.3-GHz 3-dB bandwidth around a 4.3-GHz RF, i.e., a 30% fractional bandwidth, when clocked at 250 MHz. The measured maximum delay is 1.4 ns with a 23-dB loss and noise figure; this loss or noise is orders of magnitude lower compared with fully passive linear-time-invariant RF delay lines operating at a similar frequency with the same delay. The measured IIP3 is +16 dBm. [ABSTRACT FROM AUTHOR]

In this research study, a novel hybrid approach to beam steering based on the combination of true time delay and phase shift to enable continuous beam steering with minimal beam squint in wideband mm-wave transceivers is investigated. With modern high-speed communication links in the mm-wave spectrum requiring ever higher bandwidths, and losses increasing with frequency, there is a need for steerable arrays in mobile applications. This steering capability is commonly realized by phase shifters, which enable continuous beam direction control, but produce significant beam squint at large bandwidths or steering directions. An alternative is to use a time-delayed control, which resolves the squint issue but covers only a limited number of beam directions, producing considerable loss and being large in size. This research work presents the first 2-bit time delay stage operating above 200 GHz. In addition, a novel approach is described to enable broadband continuous beam control with minimal beam squint; this is achieved by combining the time delay circuit with a 90° vector-sum phase shifter. To prove the concept, the circuit is realized in a 130-nm SiGe Bipolar Complementary Metal Oxide Semiconductor (CMOS) (BiCMOS) technology. At 4.33 mW of dc power consumption, the small-signal gain is −8.6 dB at a 3-dB band of 220–250 GHz, resulting in 12.8% of relative bandwidth. The time delay stage provides coarse beam direction control with a maximum steering angle of 43.9° resulting from a maximum delay of 1.47 ps with a resolution of 0.39 ps. Across all tuning states, the root-mean-square delay error is less than 23.7 fs. The following phase shifter enables fine direction control while also compensating ±1.5 dB of gain variation resulting from the time delay. This is achieved while reducing the area consumption to half of what is required for comparable true time delay circuits. In a minimal $2\times 1$ antenna array, this enables continuous beam direction control between ±54.6° while limiting the beam squint to less than 2.5°, equating to a more than 75% reduction in comparison to the common phase shift approach. [ABSTRACT FROM AUTHOR]

A CMOS distributed power amplifier (DPA) for quantum key distribution (QKD) system to drive an electro-optical phase modulator is developed. Due to the requirement of amplifying high-speed non-return-to-zero (NRZ) signal, our design is supposed to provide enough bandwidth, including dc. To achieve sharp roll-off performance, the m-derived filter section is applied to realize the artificial transmission line rather than the constant-k section. Combining the theory analysis and simulation, the bridges between gain ripple, group delay fluctuation, or maximum linear output power and the parameters of time domain waveform are established. Furthermore, through analyzing the attenuation and delay of the transmission line, approaches to improving the frequency performance, such as gain variation and group delay fluctuation, are provided. The DPA is implemented in the 0.25- $\mu \text{m}$ CMOS process and achieves a bandwidth of dc-12 GHz, a gain of 11.54 dB with variation of ±1.34 dB, a group delay of 400 ps with fluctuation of about 100 ps, and a maximum output 1-dB compression point of 20.6 dBm. When a 1-Gb/s NRZ signal is applied to the DPA, the rise and fall times are both about 90 ps. The amplifier occupies an area of 2.8 mm $\times0.94$ mm including pads and adopts the flip-chip package with low-temperature co-fired ceramic (LTCC) substrate. [ABSTRACT FROM AUTHOR]

This paper proposes a small‐area and low‐power all‐digital duty cycle corrector with de‐skew circuit. By adopting the proposed delay unit containing a pre‐charge transistor, half cycle delay line can accurately generate half‐cycle delay, thus ensuring that the circuit can achieve duty cycle correction with small area and low power. To achieve high‐precision clock synchronization, the proposed de‐skew circuit utilizes a high‐resolution two‐stage digital control delay line to eliminate the additional clock skew between the input clock and output clock of the circuit. The test chip is fabricated in 130 nm CMOS process and the area only occupies 0.009 mm2. The chip testing results show that duty cycle correction error is within 3.2% and phase error is less than 16 ps when input duty cycle from 20% to 80% at the frequency range from 380 MHz to 1.25 GHz. And the proposed circuit only consumes 3 mW when supply voltage is 1.2 V and clock frequency is 1 GHz. [ABSTRACT FROM AUTHOR]

A novel shared time-to-digital converter (TDC)-based, fast-locking, all-digital delay-locked loop (DLL) incorporating a duty-cycle corrector (DCC)-embedded delay line is introduced. The proposed DLL employs a shared TDC-based structure for both phase locking and duty-cycle correction operations, enabling rapid lock times of approximately 22 clock cycles. The proposed DLL offers the benefit of resolving the delay mismatch issue and achieving a rapid lock time by utilizing a shared delay line structure for both the TDC and the DCC-embedded delay line. This approach allows for high-speed operation up to 3.5 GHz. Implemented using a 65-nm 1.0-V CMOS process, the proposed DLL supports a frequency range from 0.8 to 3.5 GHz, offers a duty-cycle correction range of ±20 % at 0.8 GHz. It achieves an effective peak-to-peak output clock jitter of just 5.4 ps at 3.5 GHz, while maintaining a compact active area of 0.08 mm2 and operating with a power consumption of only 8.0 mW at 3.5 GHz. [ABSTRACT FROM AUTHOR]

This paper presents an injection-locked clock multiplier (ILCM) with a digital self-alignment frequency tracking loop (SA-FTL) to reduce the reference spur by calibrating the frequency mismatch and delay offset. To improve the power efficiency, the SA-FTL detects errors in low frequency, where the high-frequency edges from the oscillator are captured by a double-edge snapshot block. The proposed ILCM is fabricated in a 65 nm CMOS process. It has an active area of 0.045 mm 2 and consumes 3.1 mW power at 2.5 GHz output. The measured reference spur is -55.6 dB, showing a 15.9 dB improvement with the proposed SA-FTL. • An injection-locked clock multiplier (ILCM) achieves low reference spur. • The mechanism of the reference spur in the ILCM with the conventional FTL. • Capturing high-frequency edges with a double-edge snapshot block saves power. • Errors are calibrated by a digital self-alignment frequency tracking loop (SA-FTL). • The calibration runs at different phases to decouple the error sources. [ABSTRACT FROM AUTHOR]

A reconfigurable LO-generator (LOG) using an integer divider and a mixed-mode fractional divide-by-2.5 (Div2.5) is presented to generate a spurious and oscillator pulling free output spectrum without additional digital calibration for cellular narrowband Internet of Things (NB-IoT). The proposed LOG includes a fractional divider to mitigate the pulling effect between the oscillator and the power amplifier. The designed fractional Div2.5 consists of a digital Div2.5 core, a duty cycle corrector (DCC), and an I/Q generator (I/Q-GEN). An adaptive bias circuit (ADB) is applied to compensate for process, voltage, and temperature (PVT) variations on delay circuits of the DCC and the I/Q-GEN by adjusting the supply voltage. The designed LOG is fabricated in the 28-nm CMOS process while consuming 40 mW, including ADPLL, digitally controlled oscillator (DCO), local oscillator (LO) distribution buffers, and dividers at 2 GHz. The measured phase noise of the Div2.5 LOG generating 2-GHz carrier frequency is −146.3 dBc/Hz at a 10-MHz offset. The measured fractional spurious tones are below −90 dBc without oscillator pulling effects for the $1.6\sim 2.1$ -GHz output frequency. [ABSTRACT FROM AUTHOR]

The “event-driven” feature of asynchronous circuits enables the circuits to work when and where needed, making it a good alternative to design low-power circuits. However, asynchronous circuits are not widely adopted as a consequence of the lack of support by conventional EDA tools. In this article, we propose a novel design flow to implement the Click-based asynchronous bundled-data circuits efficiently down to mask layout with conventional EDA tools. To ensure timing correctness, we put forward an adaptive delay matching (ADM) method and perform accurate static timing analysis for the circuits. Compared with other asynchronous toolsets, the proposed design flow is more efficient and convenient to implement asynchronous circuits. An asynchronous convolution neural network accelerator is implemented in TSMC 180- and 65-nm CMOS process, respectively, to verify the proposed design flow. The silicon test results show that the asynchronous accelerator has 30% less power in the computing array than the synchronous one in the TSMC 65-nm CMOS process, and the energy efficiency of the asynchronous and synchronous accelerators are 1.539 TOPS/W and 1.37 TOPS/W, respectively. The energy efficiency of the asynchronous accelerator in the TSMC 180-nm CMOS process is 133 GOPS/W. [ABSTRACT FROM AUTHOR]

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A high-speed wide-range all-digital delay-locked loop (ADDLL) suitable for double data rate (DDR1)–DDR5 applications is proposed. The proposed architecture combines the advantages of synchronous mirror delay and delay-locked loop (DLL), which can solve the dynamic tracking problem without requiring a long locking time. In addition, the operating range of the aforementioned architecture is extended through harmonic locking detection and autocalibration technologies. For verification, an experimental chip was fabricated using a 90-nm standard CMOS process with a 1-V power supply. The core area occupies 381 $\mu \text {m} \times 234\,\,\mu \text{m}$. The measurement results indicate that the operating range of the proposed ADDLL was from 0.1 to 2.7 GHz, and the peak-to-peak period jitter was less than 5 ps. The output error was less than 1.9%, and the maximum quadrature phase error was 3.61°. [ABSTRACT FROM AUTHOR]

A 1.3–4-GHz quadrature-phase digital delay-locked loop (DDLL) with sequential delay control and a reconfigurable delay line is designed using a 28 nm CMOS process. The time resolution of the DDLL is reduced by updating the delay code sequentially. A bidirectional shift register enables this operation with low power, resulting in bang-bang jitter that is three times smaller than that of a conventional DDLL. Conventional delay control is replaced with sequential delay control after a DDLL lock to reduce the locking time. A DDLL with a wide operation range is achieved with a reconfigurable delay line. Unlike the conventional DDLL, the minimum delay difference is adjustable in the proposed structure. To achieve a wide frequency range, the minimum delay difference of the quadrature clock is increased or decreased in three operation modes. To compensate for local variations in the CMOS process, a skew calibration circuit is implemented with the DDLL. The hardware cost of skew calibration is minimized with the proposed DDLL because it shares the subblocks for sequential delay control. The average phase difference from the quadrature clocks becomes the reference for the 90° phase for skew correction. A duty-cycle corrector (DCC) is implemented by collecting the positive edges of the quadrature-phase clocks. The DDLL consumes 6.5 mW at the maximum clock frequency of 4 GHz. The peak-to-peak jitter is improved from 15.6 to 12.5 ps with sequential delay control. [ABSTRACT FROM AUTHOR]

In modern Digital System design, adders are widely used in many applications including Microprocessors, Digital Signal Processors, Arithmetic Logic Units and digital signal processing. Power efficiency is an important key factor for any integrated circuits. By considering the importance of Full Adder (FA) cells, their power consumption may play significant role in overall power consumption. So designing a low-power full adder is important to achieve the high-performance computing. Swing restored technique is commonly used method to reduce the signal swing at the internal nodes and it helps to reduce the power consumption and improves the circuit's speed. This paper presents a novel hybrid full adder cell design using the modified swing restored technique and complementary pass transistor logic. The Full Adder circuit was implemented using Cadence Virtuoso tool on gptk 180 nm CMOS process technology. The proposed full adder was compared with earlier reported circuits based on Delay, Power and PDP. The comparison shows that proposed circuit consumes less power with high performance. Also various process corners and noise immunity were analyzed to find the sensitivity of the circuit. Further an 8-bit Ripple Carry Adder was designed using the proposed full adder to verify the functionality in higher order bits. Simulations were performed and analyzed using the Cadence Spectre. • Designing low-power full adders is of paramount importance in modern digital system design. • The swing restored technique was employed to reduce the signal swing at the internal nodes of the full adder circuit, thereby reducing the power consumption and improving the circuit's speed. • This paper presents a novel design of a full adder circuit using the modified swing restored technique for reducing power consumption and enhancing performance. • The full adder cell introduced in this research was designed with 180 nm CMOS process technology. • A comparative study was performed between the proposed circuit and earlier reported circuits, revealing reduced power dissipation in the proposed design. [ABSTRACT FROM AUTHOR]

Recent research has revealed the possibility to achieve non-magnetic non-reciprocity using time variance. However, prior CMOS-based circulators rely on the interference between non-reciprocal switched-capacitor/transmission-line gyrators and reciprocal transmission-line rings, which increases form factor and restricts frequency tunability and bandwidth (BW). On the other hand, our recent work on quasi-electrostatic wave propagation in switched-capacitor networks has proposed a new regime in multipath switched-capacitor network operation that enables an ultra-broadband, ultra-compact reciprocal/non-reciprocal true-time-delay element. In this work, we corroborate these findings by implementing prototype devices of the quasi-electrostatic delay element. Our measurements of the delay element reveal that delays of tens of nanoseconds over hundreds of MHz BW are realizable on-chip in a compact form factor. In addition, we apply synthetic rotation across these switched-capacitor networks to realize an ultra-broadband N-port circulator with ultra-compact form factor. We implemented a wideband three-port circulator showcasing this new architecture in a standard 65-nm CMOS process. The circulator exhibits symmetric performance across all three ports and dc–1-GHz operation for a modulation frequency of 500 MHz. The measured transmission losses of the circulator range between 3.1 and 4.3 dB, matching is−15 dB, isolation is >18 dB, and noise figure (NF) is consistent with the insertion loss. This device occupies an area of 0.19 mm2 (λcenter2/1.9 × 106), representing about 100–1000 × higher miniaturization compared to the prior art. [ABSTRACT FROM AUTHOR]

This paper represents low power and high speed design issues of Hamming code generation and error detection circuit using complementary metal oxide semiconductor (CMOS) technology. Average power consumption and input to output gate delay for both Hamming code generation and error detection circuit are analyzed at 22 nm and 16 nm channel length of Metal Oxide Semiconductor (MOS) transistor. The functionality of the circuits are clarified using Tanner SPICE (T-SPICE) software. The average power consumption and input to output gate delay of the circuits are reported considering the parameters—power supply voltage, channel width to length ratio of transistors. It has been observed that whenever power supply voltage (VDD) increases, power consumption across the circuits increases, however gate delay decreases for both the circuit for fixed channel width to length ratio of the transistors. On the other hand, for fixed value of VDD if channel width to length ratio of NMOS transistor increases gate delay decreases however average power consumption increases. The variation of average power consumption and delay has also been reported with respect to KPN ratio. KPN is the ratio of channel width to length ratio of PMOS transistor to channel width to length ratio of NMOS transistor. Average power consumption is more for higher value of KPN ratio. In contrast gate delay is less at higher value KPN ratio. In this work, the values of average power consumption and gate delay are of the order of microwatt and picosecond respectively. The average power consumption of the Hamming code generation circuit in this work at 0.8 V of VDD is 0.2 µW and 1.3 µW for 22 nm and 16 nm cannel length of MOS transistor respectively. Whereas at the VDD of 0.8 V, the average power consumption of the error detection circuit is 0.4 µW and 2.3 µW respectively for 22 nm and 16 nm cannel length. The gate delay of the Hamming code generation circuit in this work at VDD of 0.8 V is 4.7 ps and 3.3 ps for for 22 nm and 16 nm cannel length of MOS transistor respectively. Also at the VDD of 0.8 V, the gate delay of the error detection circuit has been reported in this work is 16.4 ps and 12.5 ps for 22 nm and 16 nm channel length respectively. Therefore for low power and high speed Very Large Scale Integrated (VLSI) circuit design this work is applicable. [ABSTRACT FROM AUTHOR]

This brief presents an all-digital CMOS pulse-shrinking time-to-digital converter (TDC) with temperature-measuring capability for higher circuit value and cost saving. A pulse generator is proposed to generate either a time-added pulse or a temperature-sensing pulse. A cyclic delay line (DL) composed of a temperature-sensing DL and a pulse-shrinking DL becomes area efficient and achieves sufficiently wide dynamic range. A time subtractor that eliminates the effect of the offset error enhances accuracy. The proposed TDC is fabricated with TSMC 0.35- $\mu \text{m}$ CMOS process and has a small area of approximately 0.019 mm2. The effective time resolution is approximately 45 ps, with an integral nonlinearity of −0.5 to 0.85 least significant bit (LSB). The achieved temperature resolution is nearly 0.1 °C/LSB, with an inaccuracy of −1.35 °C to 0.7 °C for a range of 0 °C–90 °C. Experimental results prove that we have proposed the first TDC that successfully measures time and temperature. [ABSTRACT FROM AUTHOR]

With extreme miniaturization of traditional CMOS devices in deep sub-micron design levels, the delay of a circuit, as well as power dissipation and area are dominated by interconnections between logic blocks. Interconnect today is causing major problems such as delay, power dissipation, and so on. In an attempt to search for alternative materials, Graphene nanoribbons have been found to be potential for both transistors and interconnects due to its outstanding electrical and thermal properties. Graphene nanoribbons provide better options as materials used for global routing trees in VLSI circuits. However, certain special characteristics of Graphene nanoribbon prohibit direct application of existing VLSI routing tree construction methods. In this article, we address this issue and propose heuristic methods for construction of Graphene nanoribbon-based minimum hybrid cost and minimum-delay Steiner trees. We compute the delays for the trees using Elmore delay approximation. Experimental results demonstrate the effectiveness of our proposed methods, which are quite encouraging. [ABSTRACT FROM AUTHOR]

This article reports a time-domain smart temperature sensor using current starved inverters (CSIs) and switched ring oscillator-based time-to-digital converter (SRO-TDC) in a standard 180 nm CMOS process. A novel temperature-to-time converter (TTC) is proposed using complementary delay lines, which are designed by utilising CSIs. The proportional to absolute temperature delay line offers a temperature coefficient (TC) of 615 ppm/ ∘ C , whereas the complementary to absolute temperature delay line possesses a TC of 300 ppm/ ∘ C , over 0–100 ∘ C temperature range. A novel multipath delay cell-based coupled oscillator is proposed for SRO-TDC. The proposed SRO-TDC operates as readout circuit for the sensor, which achieves 30 ns range at 12 ps resolution. The uncertainty of the sensor is limited to ± 0.63 ∘ C , after the 2-point calibration at 20 ∘ C and 80 ∘ C , which is because of complementary delay lines in TTC and noise shaping behaviour of the SRO-TDC. The sensor achieves 0.4 μ s conversion time at 0.04 ∘ C resolution. [ABSTRACT FROM AUTHOR]

This paper presents a new technique to design switchable true time delay (TTD) lines using periodic shunt open-stubs, shorter than a quarter wavelength at the highest frequency of interest. Structural parameters are obtained by minimizing the group delay variation and maximizing the return loss over the operating band. Advantages of the proposed design are low insertion loss, higher 1 dB compression point, and less number of switches compared to the conventional designs. To verify the proposed technique, 2-states and 8-states TTD lines are fabricated for L- and S-band applications. For the 8-states delay networks, measured insertion losses are smaller than 1.9 dB at 3 GHz. Return losses are more than 10 dB over 1–4 GHz band. Measured maximum time delay is 84 ps for the 8-states delay lines with a step size of 10 ps. All the TTDs operate as linear device at least up to 23 dBm. [ABSTRACT FROM AUTHOR]

A wideband integrated delay chain chip with 5-bit main delay control, two error correction bits, maximum delay of 125- and 3.9-ps delay resolution, designed and fabricated in a 0.18- $\mu \text{m}$ CMOS technology is presented. This delay chain is a cascade of seven passive internal-switched delay blocks which the five main bits are based on novel delay structures. The proposed delay structures are similar to second-, fourth-, and sixth-order all-pass networks and are robust to mismatch effects of resistive parasitics of transistor switches. Measurement results of the fabricated delay chain show 15.2–23.3-dB insertion loss and less than 3.3-ps rms delay error over the intended frequency band from 8–18 GHz. Input and output reflection coefficients are better than −11 dB for the delay chain including the effect of RF bondwires and pads. The fabricated chip occupies an area of $2.0\times 1.0$ mm2 and has no dc power consumption. [ABSTRACT FROM AUTHOR]

An all-digital CMOS (Complementary Metal-Oxide Semiconductor) pulse-shrinking smart temperature sensor (PSSTS) is proposed to deliver the merits of area efficiency, improved accuracy, and high resolution. First, an inverter-based temperature-sensing delay line generates a pulse with a width proportional to absolute temperature (PTAT). Then, a pulse-shrinking delay line (PSDL) with a pulse-mixing scheme (PMS) measures the PTAT pulse through pulse shrinking. The two delay lines become area efficient when the channel length of transistors is long. Conventionally, the area-efficient PSDL decreases the time resolution. Thus, the all-digital PMS considerably enhances the time resolution and achieves an excellent sensor resolution. Finally, a time subtractor improves sensor accuracy by effectively eliminating the offset error effects. The proposed sensor was implemented in a Taiwan Semiconductor Manufacturing Company 0.35-μm CMOS process and occupied an area of 0.0247 mm2, which is the best area among related studies. The PSSTS exhibited an improved inaccuracy from a maximal inaccuracy of 1.95 °C to 1.5 °C and an excellent resolution of approximately 0.05 °C/LSB. Experimental results prove that this study is area-efficient and achieves improved accuracy and high resolution. [ABSTRACT FROM AUTHOR]

This study presents the design and implementation of a compact and wideband active variable true-time delay line for timed array applications. Using a combination of coarse delay cells and fine delay cells, the proposed delay line achieves a large delay range and a high delay tuning resolution. Instead of LC delay lines or transmission lines, the delay can be approximated by compact active filters using transconductors and capacitors. The coarse delay cell adopts inductive peaking to broaden the bandwidth, and the fine delay cell employs a novel differential active inductor to improve the delay resolution and integration level. The group delays of the coarse delay cells and fine delay cells are analyzed and optimized. The signal transmission path is controlled by path-selection amplifiers and V–I conversion switches to achieve delay variability. The delay time is calibrated by the delay-locked loop (DLL) to mitigate the process, voltage and temperature variations. The complementary metal-oxide-semiconductor (CMOS) variable true-time delay line is fabricated in a 0.18-μm CMOS process. Experiments indicate that the maximal relative delay is 95 ps and that the delay resolution is 5 ps within a 10% delay variation over a frequency range of 0.6–4.2 GHz. The chip dissipates 88 mW under a 1.8-V supply, and the core area including the DLL circuit is only 0.05 mm2. [ABSTRACT FROM AUTHOR]

This paper presents a rotatable cyclic Vernier digital-to-time converter (DTC) with 1.8 ps timing resolution on an 80 ns time scale. The proposed DTC features high timing resolution, and can be utilized in beam-steering arrays, which is infeasible for ordinary Vernier DTCs. The proposed DTC was implemented within a passive time-equivalent direct-sampling ultra-wideband impulse-radio radar system and was fabricated in 65 nm CMOS technology. This radar system is capable of quantizing direct-sampled impulse waveforms to provide full degrees of freedom for backend digital signal processing. The measured differential nonlinearity/integral nonlinearity of the DTC was +4.6/−3 and 12.4/−9.4 where the LSB was 1.8 ps, and the total power consumption was 133 mW. Also, a new method for localization between wireless sensor nodes of equivalent-time direct-sampling radar is presented in this paper; this method can theoretically achieve resolution as high as that of regular radar. [ABSTRACT FROM PUBLISHER]

NAND-based digitally controlled delay-lines (DCDLs) are employed in several applications owing to their excellent linearity, good resolution and easy standard cell design. A glitch-free DCDL behavior is often a strict requirement [e.g. spread-spectrum clock generators (SSCG) and digitally controlled oscillators]. Existing glitch-free NAND-based DCDL topologies either require two flip-flops for each DCDL delay-element (DE) or present a very long settling time which limits the maximum working frequency. This paper proposes a novel glitch-free NAND-based DCDL that joins the advantages of previously proposed topologies: uses only a single flip-flop for each DE (reducing area and power) and has relaxed timing requirements (allowing easy integration in applications like SSCG). In the paper, the glitch-free operation of the proposed circuit is firstly demonstrated theoretically and then verified experimentally, with the help of an SSCG built using proposed DCDL and implemented in 28 nm CMOS. Simulation results show that proposed DCDL results in a more that 30 % reduction of the power dissipation and a >20 % reduction in area occupation with respect to double flip-flop DCDL, without any timing constraints penalty. [ABSTRACT FROM AUTHOR]

A 100-MHz–2-GHz closed-loop analog in-phase/ quadrature correction circuit for digital clocks is presented. The proposed circuit consists of a phase-locked loop- type architecture for quadrature error correction. The circuit corrects the phase error to within a 1.5° up to 1 GHz and to within 3° at 2 GHz. It consumes 5.4 mA from a 1.2 V supply at 2 GHz. The circuit was designed in UMC 0.13- \mu \textm mixed-mode CMOS with an active area of 102\,\,\mu \mathrm m \times 95\,\,\mu \mathrm m . The impact of duty cycle distortion has been analyzed. High-frequency quadrature measurement related issues have been discussed. The proposed circuit was used in two different applications for which the functionality has been verified. [ABSTRACT FROM PUBLISHER]

Current mode is a popular CMOS-based implementation of threshold logic functions, where the gate delay depends on the sensor size. This paper presents a new implementation of current mode threshold functions for improved gate delay and switching energy. An analytical method is also proposed in order to identify quickly the sensor size that minimizes the gate delay. Simulation results on different gates implemented using the optimum sensor size indicate that the proposed current mode implementation method outperforms consistently the existing implementations in delay as well as switching energy. [ABSTRACT FROM PUBLISHER]

This paper presents a new all-digital CMOS digital-to-time converter (DTC) based on pulse expansion. Pulse expansion is achieved using an all-digital pulse-mixing scheme that can effectively improve the timing resolution and enable the DTC to be concise. Without requiring the Vernier principle or a costly digital-to-analog converter, the DTC comprises a pulse generator for generating a pulse, a pulse expanding circuit (PEC) for programming timing generation, and a time subtractor for removing the time width of the pulse. The PEC comprises only a delay chain composed of proposed pulse-expanding units and a multiplexer. For accuracy enhancement, a pulse neutralization technique is presented to eliminate undesirable pulse variation. A 4-bit converter was fabricated in a 0.35-μm Taiwan Semiconductor Manufacturing Company CMOS process and had a small area of nearly 0.045 mm2. Six chips were tested, all of which exhibited an improved resolution (approximately 16 ps) and low integral nonlinearity (less than ±0.4 least significant bit). The power consumption was 0.2 mW when the sample rate was 1M samples/s and the voltage supply was 3.3 V. The proposed DTC not only has favorable cost and power but also achieves an acceptable resolution without requiring an advanced CMOS process. This study is the first to use pulse expansion in digital-to-time conversion. [ABSTRACT FROM AUTHOR]

This paper presents a prototype of a 16-channel Time-to-Digital Converter (TDC) based on the coarse-fine architecture for a small animal Position Emission Tomography (PET) system, which achieves both a large measurement range and high precision. The coarse time stamp is provided by two 12-bit counters, and the duplication of hardware is intended to avoid metastability when the hit signal edge is close to the edge of the counter clock. The fine time stamp is realized with a tunable delay line, which is adjusted by a 32-stage Delay-Locked Loop (DLL) and provides submultiples of the counter clock period. The device has been designed and fabricated in a 180 nm CMOS process. With a 200 MHz system clock, the full-scale measurement range is 20. 48 μ s and the fine bin size is 156 ps. The test results show that the differential nonlinearity (DNL) is between −0.2 to ＋0.2 LSB, and the and integral nonlinearity (INL) is within the range of −0.5 to 0.2 LSB for all 16 channels. The one-shot time precision is better than 60 ps RMS. Power consumption of each channel is less than 8 mW. [ABSTRACT FROM AUTHOR]

A four-phase all-digital delay-locked loop (ADDLL) with a de-skew circuit for NAND Flash high-speed interfaces is proposed. The proposed de-skew circuit adopts a fall-edge-judgment phase adjuster and a three-stage digitally controlled delay line to align the system input clock and 0 ∘ output clock of the four-phase DLL over a wide frequency range, thus solving the four-phase offset caused by clock skew. A parallel-cascade configuration is proposed to solve the variable phase alignment problem caused by mode switching, thus effectively improving the phase-locked accuracy. The proposed circuit is fabricated in the 0.13 μ m CMOS process with a 0.072 mm 2 core area. The chip testing results show an operating frequency range from 26 MHz to 1.55 GHz and a typical alignment error of approximately 17 ps. [ABSTRACT FROM AUTHOR]

We present the design, implementation, and test results of an integrated time digitizer based on a new conversion method that applies multiedge coding in independent coding lines. The proposed method eliminates an existing technological limitation of resolution inherent in the methods based on standard time coding delay lines, which causes that the value of resolution cannot be lower than the propagation time of the fastest delay element in the line. The developed method allows increasing the resolution proportionally to the number of signal edges coded and lines involved. An interpolating time counter designed by applying the six-edge coding in three independent coding lines provides subpicosecond resolution (902 fs), high precision (<6 ps), and wide measurement range (2 s). A short conversion time of the method and the use of local RAM memory for storing measurement results allowed for significant shortening of the digitizer dead time and achieving the measurement rate up to 6 million measurements per second. The digitizer is implemented in an easily available and cheap field programmable gate array device manufactured in the 45-nm CMOS technology. [ABSTRACT FROM PUBLISHER]

In this paper, an all-digital delay-locked loop (ADDLL) with a phase-tracing delay unit (PTDU) has been proposed to achieve wide-operating frequency range, low power, and low cost. For the wide-range DLL, the long delay line is replaced by a PTDU which includes two gated ring oscillators (GROs) for generating the wide delay range with a reduced die area. According to the dual-loop control scheme in this work, the input clock rising edge and falling edge are tracked independently to ensure that the ADDLL output maintains the duty cycle of the input reference. Furthermore, the ADDLL utilizes an open-loop scheme to achieve fast lock time of five clock cycles for all supported input frequencies. The proposed ADDLL has been fabricated in TSMC 90 nm CMOS technology and supports a wide-operating frequency range from 6.7 MHz to 1.24 GHz within a small active area of 0.0318\;\text mm^2. The measured peak-to-peak and root-mean-square jitter at 1.24 GHz are 2.22 ps and 424.62 fs, respectively. The ADDLL consumes 14.5 mW while operating at 1.24 GHz. [ABSTRACT FROM PUBLISHER]

In this paper, we present a carry skip adder (CSKA) structure that has a higher speed yet lower energy consumption compared with the conventional one. The speed enhancement is achieved by applying concatenation and incrementation schemes to improve the efficiency of the conventional CSKA (Conv-CSKA) structure. In addition, instead of utilizing multiplexer logic, the proposed structure makes use of AND-OR-Invert (AOI) and OR-AND-Invert (OAI) compound gates for the skip logic. The structure may be realized with both fixed stage size and variable stage size styles, wherein the latter further improves the speed and energy parameters of the adder. Finally, a hybrid variable latency extension of the proposed structure, which lowers the power consumption without considerably impacting the speed, is presented. This extension utilizes a modified parallel structure for increasing the slack time, and hence, enabling further voltage reduction. The proposed structures are assessed by comparing their speed, power, and energy parameters with those of other adders using a 45-nm static CMOS technology for a wide range of supply voltages. The results that are obtained using HSPICE simulations reveal, on average, 44% and 38% improvements in the delay and energy, respectively, compared with those of the Conv-CSKA. In addition, the power–delay product was the lowest among the structures considered in this paper, while its energy–delay product was almost the same as that of the Kogge–Stone parallel prefix adder with considerably smaller area and power consumption. Simulations on the proposed hybrid variable latency CSKA reveal reduction in the power consumption compared with the latest works in this field while having a reasonably high speed. [ABSTRACT FROM AUTHOR]

Due to their provably capacity-achieving performance, polar codes have attracted a lot of research interest recently. For a good error-correcting performance, list successive-cancellation decoding (LSCD) with large list size is used to decode polar codes. However, as the complexity and delay of the list management operation rapidly increase with the list size, the overall latency of LSCD becomes large and limits the applicability of polar codes in high-throughput and latency-sensitive applications. Therefore, in this work, the low-latency implementation for LSCD with large list size is studied. Specifically, at the system level, a selective expansion method is proposed such that some of the reliable bits are not expanded to reduce the computation and latency. At the algorithmic level, a double thresholding scheme is proposed as a fast approximate-sorting method for the list management operation to reduce the LSCD latency for large list size. A VLSI architecture of the LSCD implementing the selective expansion and double thresholding scheme is then developed, and implemented using a UMC 90 nm CMOS technology. Experimental results show that, even for a large list size of 16, the proposed LSCD achieves a decoding throughput of 460 Mbps at a clock frequency of 658 MHz. [ABSTRACT FROM AUTHOR]

This paper presents a high resolution time-to-digital converter (TDC) architecture, which combines the advantages of sub-ranging and Vernier delay line TDCs. In the proposed TDC, the time input is converted to a digital code in a coarse–fine manner by two stages of parallel delay lines. Both stages have coarse (but slightly different) time resolutions. The effective fine resolution of the second stage is achieved by making it work with the first stage in a Vernier manner. To alleviate the linearity problem caused by random variations of the delays of the delay elements, a foreground DNL calibration technique is proposed. A proof-of-the-concept Vernier sub-ranging (3+3)-bit TDC was designed and fabricated in a 0.13-μm CMOS process. It demonstrates a resolution of 5 ps, a DNL of 0.6 LSB and a single-shot precision of 0.4 LSB at a conversion rate of 10 Msps while consuming 1.15 mW from 1.2 V at a conversion rate of 20 Msps. [ABSTRACT FROM AUTHOR]

A low-power hybrid digital pulse width modulator (DPWM) is proposed in the paper. Owing to the piecewise calibration scheme, the delay time of delay line is locked to target frequency. The delay line consists of two piecewise lines with different control codes. The delay time of each cell in one sub-delay-line is longer than the last significant bit (LSB) of DPWM, while the delay time of each cell in the other sub-delay-line is shorter than LSB. Optimum linearity is realised with minimum standard cells. Simulation results show that the differential nonlinearity and integral nonlinearity are improved from 5.1 to 0.4 and from 5 to 1.3, respectively. The DPWM is fully synthesised and fabricated in a 90-nm CMOS process. The proposed DPWM occupies a silicon area of 0.01 mm2, with 31.5 μw core power consumption. Experimental results are shown to demonstrate the 2-MHz, 10-bit resolution implementation. Pulse width histogram is firstly introduced to characterise the linearity of the DPWM. [ABSTRACT FROM PUBLISHER]