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Angular single-event (SE) mechanisms and experimental upset data for 14-/16-nm bulk fin field-effect transistor (FinFET) technologies are presented and analyzed. The discrete structure of FinFETs introduces unique geometrical and orientation dependences for angular SE mechanisms and SE upset (SEU) responses of FinFET circuits. Geometric analyses and 3-D technology computer-aided design results effectively explain the angular mechanisms behind experimentally observed SE crosssectional responses. Results show that angular SEU crosssectional characteristics can be attributed to the proportional contributions of charge deposition regions in the fin structure and the subfin bulk substrate. [ABSTRACT FROM PUBLISHER]

A marked state dependence and significant reduction in SEU cross section with even small increases in incident angle are reported in an asymmetric RC-hardened 90 nm CMOS SRAM. The effects are attributable to the bias dependence and high aspect ratio of the deep trench capacitor sidewall depletion region, exacerbated by process-induced boron depletion. The asymmetric implementation, using capacitive hardening in only one leg of the SRAM cell, led to the appearance of the effect in experimental results. [ABSTRACT FROM PUBLISHER]

Measured results and 3D TCAD simulations demonstrate that narrow, long channel PDSOI devices may exhibit a total-ionizing-dose response more like FDSOI devices, attributable to regions of lighter body doping and trapped charge in the isolation regions. [ABSTRACT FROM PUBLISHER]

Heavy-ion and two-photon-absorption (TPA) experiments have been performed on ultra-thin implant-free quantum well SiGe channel pMOSFETs. Both the single-event-transient pulse magnitude and polarity can depend strongly on the location of the strike along the device channel. The polarity inversion occurs primarily because very limited transient charge collection occurs below the quantum well, as confirmed by two-dimensional TCAD simulation. [ABSTRACT FROM PUBLISHER]

A circuit-level layout-aware single-event simulation capability is presented. Multiple 40-nm bulk CMOS flip-flops are analyzed to determine single-event upset (SEU) sensitive area. Comparisons between simulation results and broadbeam heavy-ion test data show excellent agreement. Simulations of single-event strikes over the entire flip-flop layout can be performed in less than 1 h. [ABSTRACT FROM PUBLISHER]

SEU simulation analyses of a commercial 45 nm CMOS SOI SRAM cell compared to test data highlight the need to better understand and account for variation in inter-cell hardness, and uncertainty in energy deposition in small sensitive volumes. Simulations indicate that operating voltage and body resistance have the largest impact on simulated cell hardness. [ABSTRACT FROM AUTHOR]

As integrated circuits become smaller and more complex, it has become increasingly difficult to simulate their responses to radiation. The distance and time scales of relevance extend over orders of magnitude, requiring a multi-scale, hierarchical simulation approach. This paper demonstrates the use of multi-scale simulations to examine two radiation-related problems: enhanced low-dose-rate sensitivity (ELDRS) in bipolar transistors and single-event effects (SEE) in CMOS integrated circuits. Examples are included that demonstrate how information can be passed from simulation tools operating at one level of abstraction to those operating at higher levels, while maintaining accuracy and gaining insight. [ABSTRACT FROM AUTHOR]

Structures integrated onto a BiCMOS test chip are specially designed to characterize the complex mechanisms related to proton radiation response in bipolar technologies. Bipolar devices from a commercial process are modified to include independent gate terminals. Through the use of gate control, the effects of proton-induced defects on discrete bipolar devices and analog bipolar circuits can be analyzed independently, thereby facilitating a quantitative description of the nonlinear relationship between the radiation defects and electrical response at both the device and circuit level. [ABSTRACT FROM AUTHOR]