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Increased process variability and reliability issues present a major challenge for future SRAM trends. Non-intrusive and accurate SRAM stability measurement is crucial for estimating yield in large SRAM arrays. Conventional SRAM variability metrics require including test structures that cannot be used to investigate cell bit fails in functional SRAM arrays. This work proposes the Word Line Voltage Margin (WLVM), defined as the maximum allowed word-line voltage drop during write operations, as a metric for the experimental characterization of write stability of SRAM cells. Their experimental measurement can be attained with minimal design modifications, while achieving good correlation with existing writability metrics. To demonstrate its feasibility, the distribution of WLVM values has been measured in an SRAM prototype implemented in 65 nm CMOS technology. The dependence of the metric with the width of the transistors has been also analysed, demonstrating their utility in post-process write stability characterization. [ABSTRACT FROM AUTHOR]

This work proposes a methodology to estimate the statistical distribution of the probability that a 6T bit-cell starts up to a given logic value in SRAM memories for PUF applications. First, the distribution is obtained experimentally in a 65-nm CMOS device. As this distribution cannot be reproduced by electrical simulation, we explore the use of an alternative parameter defined as the distance between the origin and the separatrix in the bit-cell state space to quantify the mismatch of the cell. The resulting distribution of this parameter obtained from Monte Carlo simulations is then related to the start-up probability distribution using a two-component logistic function. The reported results show that the proposed imbalance factor is a good predictor for PUF-related reliability estimation with the advantage that can be applied at the early design stages. [ABSTRACT FROM AUTHOR]

Abstract: We analyze and compare the impact of radiation-induced transient effects based on evaluating the critical charge parameter for 6T and 8T SRAMs during hold, read and write operations. Results on a commercial 65nm CMOS technology show that 6T and 8T cells offer quite similar robustness when they are in hold. However, the critical charge observed in other operation modes is reduced a 55% respect to the hold operation. For this reason, we provide a thorough analysis of the critical charge behavior in 6T and 8T SRAMs to determine the dependence of memory radiation robustness with memory state. Single event upsets and single event transients have been considered in the analysis, showing that 8T have better performance than 6T. The dependence of critical charge with memory state for high workload memories modifies the overall memory SER estimation indicating the significance of analyzing the memory robustness as a memory state function. In general, the SER estimation results show that the robustness behavior of 8T-based cells is better than robustness behavior of 6T-based cells. [Copyright &y& Elsevier]