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Your search keyword '"Perenzoni, M."' showing total 3 results
Start Over Author "Perenzoni, M." Topic cmos integrated circuit
3 results on '"Perenzoni, M."'

1. Small area 0.3 pJ/conv, 45 ps time‐to‐digital converter for arrays of silicon photomultiplier interfaces in 150 nm CMOS.

Author

Perenzoni, M., Xu, H., and Stoppa, D.

Abstract

A ring‐oscillator‐based time‐to‐digital converter (TDC) is presented which can achieve a figure‐of‐merit of 0.3 pJ/conv in a very small footprint of 0.0024 mm2. Thanks to the optimisation of the ring‐oscillator and of the sub‐cycle interpolation, a 45‐ps LSB is obtained with only 0.95 mW of power consumption. The area and power characteristics make the TDC suitable for its use in repeated instances, such as in multiple silicon photomultipliers readout channels or single‐photon imaging devices with time‐correlated detection. [ABSTRACT FROM AUTHOR]

Published
2015
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2. A systematic design procedure for high-speed opamp performance optimization

Author

Andrea Baschirotto, Matteo Perenzoni, F. De Nisi, M. Malfatti, David Stoppa, Perenzoni, M, Malfatti, M, De Nisi, F, Stoppa, D, and Baschirotto, A

Subjects
Engineering, Settling time, two-stage class AB opamp, 0.35 micron, Integrated circuit design, Die (integrated circuit), 0.87 mW, law.invention, integrated circuit design, law, Electronic engineering, 3.3 V, CMOS integrated circuit, operational amplifier, systematic design, business.industry, power consumption, 49 MHz, high-speed opamp performance optimization, CMOS technology, CMOS, Power consumption, Operational amplifier, business, 43 n, imager readout
Abstract

This work introduces a design procedure for two-stage class AB opamps which minimizes power consumption for a given specifications set. The proposed procedure has been applied to the redesign of published opamps for comparison target, demonstrating the procedure validity by improving their efficiency. The systematic procedure is then applied to an opamp that will be part of the readout of an imager. The opamp is designed in a 0.35 /spl mu/m 3.3V standard CMOS technology and exhibits GBW /spl equiv/49MHz, SR /spl equiv/ 74V//spl mu/s, 0.1% settling time of 43ns, consuming only 0.87mW with a die area of 0.0053mm/sup 2/.

Published
2005

3. A complete front-end system read-out and temperature control for resistive gas sensor array

Author

A. Simoni, L. Lorenzelli, M. Malfatti, Matteo Perenzoni, N. Viarani, Andrea Baschirotto, Malfatti, M, Perenzoni, M, Viarani, N, Simoni, A, Lorenzelli, L, and Baschirotto, A

Subjects
Materials science, read out circuit, 0.35 micron, Die (integrated circuit), resistance-to-period converter, substrate temperature control circuit, gas sensor, Sensor array, 3.3 V, 30 mW, readout electronic, 100 C, CMOS integrated circuit, 0.3 to 300 Mohm, Front-end, Resistive touchscreen, resistive gas sensor array, Temperature control, resistance measurement, business.industry, Electrical engineering, CMOS technology, Microcontroller, Temperature gradient, CMOS, 150 to 350 C, microcontroller, front end system read-out, business, Voltage
Abstract

A complete front-end system for resistive gas sensor array is presented. The system is composed by a substrate temperature control circuit and by a read-out circuit. The temperature control allows maintaining a 100/spl deg/C temperature gradient selected in the temperature range [150/spl deg/C-350/spl deg/C] on the array of sensor. The gas sensor read-out circuit, which acts like a resistance-to-period converter, is suitable to be interfaced to a microcontroller in order to achieve a resolution error lower than 0.5% for a resistance ranging in (300k/spl Omega/-300M/spl Omega/]. The full device, including 8 read-out channels and 2 temperature control systems, is designed in a standard 0.35/spl mu/m CMOS technology. The die area is 1.8mm/sup 2/ with a total power consumption of 30mW from a single 3.3V supply voltage.

Published
2005

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