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This brief presents a new design methodology of single-chip reconfigurable CMOS RF power amplifier (PA) supporting both dual-band and multi-power-mode operation. The proposed architecture utilizes a novel switched-capacitor based output network to facilitate differential signal combining and impedance transformation at two widely separated frequency bands. It can offer three distinct output power levels (saturation) to be selected for multi-power-mode applications. Besides, closed-form explicit equations are readily available for the evaluation of component values. For verification, a PA operating at 1.8/2.6 GHz (non-concurrent), with three distinct saturation power levels (21, 23, 26 dBm) and peak efficiency of about 30%, is designed and fabricated using $0.35~{\mu }\text{m}$ CMOS process. [ABSTRACT FROM AUTHOR]

In this study, a parallel-segmented complementary metal-oxide–semiconductor (CMOS) step-up autotransformer was developed to improve the impedance transformation ratio. In addition, a corresponding scalable segmentation-based model was developed on a CMOS case. The proposed segmentation-based model was used to predict the accurate performance of a parallel-segmented autotransformer. The parallel-segmented step-up autotransformer was fabricated through a standard 65 nm CMOS process. The modeled results showed good agreement with the measured results. The implemented one/two parallel-segmented CMOS step-up autotransformer changed the impedance from 50 Ω to 9.5 Ω/6.1 Ω with −1.21 dB/−1.54 dB minimum insertion loss at 3 GHz. [ABSTRACT FROM AUTHOR]

In this paper, an adaptive N-path filter design technique is presented. The filter designed by this method can be reconfigured to different shapes, e.g., Butterworth or Chebyshev with variable bandwidth (BW), based on the user requirements. In addition, an analytical synthesis procedure is introduced to realize high-order bandpass filters (BPFs) based on N-path architecture with a prescribed set of specifications. A proof-of-concept BPF is fabricated and measured in a 65-nm CMOS process. The filter can be reconfigured to realize different filter shapes by changing coupling capacitors. The BW of the proposed filter is also tunable. The passband of the filter is tunable from 0.2 to 1.2 GHz with a gain of 14.5–18 dB, a noise figure of 3.7–5.5 dB, and a total power consumption of 37.5–52.7 mW. The channel BW can be varied from 20 to 40 MHz and the filter out-of-band third-order intercept point ( $\Delta f=50$ MHz) is 25 dBm. [ABSTRACT FROM AUTHOR]

In this paper, we propose a design method of multi-way combining networks with impedance transformation for millimeter-wave (MMW) power amplifiers (PAs) to achieve high output power and wideband performance simultaneously in millimeter-wave frequency. Based on the proposed methodology, three power amplifiers are designed and fabricated in V-band, W-band, and D-band using 65-nm CMOS technology. With 1.2-V supply, the saturation powers of these power amplifiers are 23.2 dBm, 18 dBm and 13.2 dBm at 64 GHz, 90 GHz, and 140 GHz, with 25.1-GHz, 26-GHz, and 30-GHz 3-dB bandwidth, respectively. Compared with the published MMW amplifiers, these PAs achieve high output power and wide band performances simultaneously, and the ouput power levels is the state-of-the-art performance at these frequencies. [ABSTRACT FROM AUTHOR]

A super-heterodyne receiver utilizing integrated high-Q filters to condition the desired signal to be digitized by a bandpass ADC at an IF of 110 MHz achieves a NF of 2.8 dB and an IIP3 of -8.4 dBm. The conventional M-phase filter is developed to a new form of high-Q filter that is centered at sum or difference of two clocks. The M-phase filter is also evolved to take two quadrature inputs to perform image rejection, while exhibiting a high-Q bandpass response with desired signal located in the center. Built of inverters, switches, and MOS capacitors, the receiver follows technology scaling and is reconfigurable through a clock. The receiver including the dividers and LO path draws 12 mA of battery current and occupies 0.76 mm^2 in 65-nm CMOS. [ABSTRACT FROM AUTHOR]

A quad-band 2.5G receiver is designed to replace the front-end SAW filters with on-chip bandpass filters and to integrate the LNA matching components, as well as the RF baluns. The receiver achieves a typical sensitivity of -110 dBm or better, while saving a considerable amount of BOM. Utilizing an arrangement of four baseband capacitors and MOS switches driven by 4-phase 25% duty-cycle clocks, high-Q BPF's are realized to attenuate the 0 dBm out-of-band blocker. The 65 nm CMOS SAW-less receiver integrated as a part of a 2.5G SoC, draws 55 mA from the battery, and measures an out-of-band 1 dB-compression of greater than +2 dBm. Measured as a stand-alone, as well as the baseband running in call mode in the platform level, the receiver passes the 3GPP specifications with margin. [ABSTRACT FROM AUTHOR]

A transformer-based high-order output matching network is proposed for broadband power amplifier design, which provides optimum load impedance for maximum output power within a wide operating frequency range. A design methodology to convert a canonical bandpass network to the proposed matching configuration is also presented in detail. As a design example, a push-pull deep class-AB PA is implemented with a third-order output network in a standard 90 nm CMOS process. The leakage inductances of the on-chip 2:1 transformer are absorbed into the output matching to realize the third-order network with only two inductor footprints for area conservation. The amplifier achieves a 3 dB bandwidth from 5.2 to 13 GHz with +25.2 dBm peak Psat and 21.6% peak PAE. The EVM for QPSK and 16-QAM signals both with 5 Msample/s are below 3.6% and 5.9% at the output 1 dB compression point. This verifies the PA's capability of amplifying a narrowband modulated signal whose center-tone can be programmed across a large frequency range. The measured BER for transmitting a truly broadband PRBS signal up to 7.5 Gb/s is less than 10^-13, demonstrating the PA's support for an instantaneous wide operation bandwidth. [ABSTRACT FROM AUTHOR]

This article proposes an efficient power-combining architecture with differential and single-ended power amplifiers (PAs) in a CMOS process. The single-ended amplifier is added for overall efficiency enhancement. To demonstrate this concept, a CMOS PA using the proposed architecture was fabricated with a 0.13-μm CMOS technology that delivers 30.6 dBm of output power with 42% drain efficiency and 38% power-added efficiency at 1.95 GHz. © 2010 Wiley Periodicals, Inc. Microwave Opt Technol Lett 52:2214–2217, 2010; Published online in Wiley InterScience (www.interscience.wiley.com). DOI 10.1002/mop.25460 [ABSTRACT FROM AUTHOR]

A tournament-shaped magnetically coupled power-combiner architecture for a fully integrated RF CMOS power amplifier is proposed. Various 1 : 1 transmission line transformers are used to design the power combiner. To demonstrate the new architecture, a 1.81-GHz CMOS power amplifier using the tournament-shaped power combiner was implemented with a 0.18-μm RF CMOS process. All of the matching components, including the input and output transformer, were fully integrated. The amplifier achieved a drain efficiency of 38% at the maximum output power of 31.7 dBm. [ABSTRACT FROM AUTHOR]