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This paper describes a 3 to 5 GHz frequency synthesizer for MB-OFDM (multi-band OFDM) UWB (Ultra- Wideband) application using 0.13 um CMOS process. The frequency synthesizer operates in the band group 1 whose center frequencies are 3432 MHz, 3960 MHz, and 4488 MHz. To cover the overall frequencies of group 1, an efficient frequency planning minimizing a number of blocks and the power consumption are proposed. And, a high-frequency VCO and prescaler architecture are also presented in this paper. A new coarse tuning scheme that utilizes the MIM capacitance and the varactor is proposed to expand the VCO tuning range. The single PLL and two SSB-mixers consume 75 mW from a 1.5 V supply. The VCO tuning range is 500 MHz. The simulated phase noise of the VCO is -110 dBc/Hz at 1 MHz offset. The die area is 3 times 2 mm2.

This paper describes a 3 to 5 GHz frequency synthesizer for MB-OFDM (multi-band OFDM) UWB (Ultra-Wideband) application using 0.13 um CMOS process. The frequency synthesizer operates in the band group 1 whose center frequencies are 3432 MHz, 3960 MHz, and 4488 MHz. To cover the overall frequencies of group 1, an efficient frequency planning minimizing a number of blocks and the power consumption are proposed. And, a high-frequency VCO and prescaler architecture are also presented in this paper. A new coarse tuning scheme that utilizes the MIM capacitance and the varactor is proposed to expand the VCO tuning range. The single PLL and two SSB-mixers consume 75 mW from a 1.5 V supply. The VCO tuning range is 500 MHz. The simulated phase noise of the VCO is -110 dBc/Hz at 1 MHz offset. The die area is 3 x 2 mm2.

This paper presents a fast switching CMOS frequency synthesizer with a new coarse tuning method for PHS applications. To achieve the fast lock-time and the low phase noise performance, an efficient bandwidth control scheme is proposed. Charge pump up/down current mismatches are compensated with the current mismatch compensation block. Also, the proposed coarse tuning method selects the optimal tuning capacitances of the LC-VCO to optimize the phase noise and the lock-time. The measured lock-time is about 20 mus and the phase noise is - 121dBc/radicHz at 600kHz offset. This chip is fabricated with 0.25mum CMOS technology, and the die area is 0.7mm times 2.1mm. The power consumption is 54mW at 2.7V supply voltage