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This paper presents a wide dynamic range (DR) CMOS root-mean-square power detector with a temperature variation compensation technique in a 28-nm CMOS process. The cascaded gain amplifiers and squaring circuits in the proposed power detector can achieve wide DR with the power level segmented detection method using a switch driver with the help of a modem. A 12-bit current digital-to-analog converter is used to calibrate dc offset in the power detector with 25- $\mu{\hbox{V}}$ steps to improve the accuracy. Measured DR is more than 40 dB from 700 MHz to 4 GHz. A temperature compensation bias circuit improves the performance of the detector with maximum 0.8-dB error over the temperature range $-{\hbox{30 }}^{\circ}{\hbox{C}}\sim {\hbox{90 }}^{\circ}{\hbox{C}}$ . The chip area is 333 $ \mu{\hbox{m}}\times$ 450 $\mu{\hbox{m}}$ and the power consumption is from 5.8 to 11.8 mW depending on the input power using a 1.8-V power supply.

As LTE offers the best wireless experience as never before, people spend much more time on smartphones to enjoy internet surfing and social networking, etc. To further improve the LTE network efficiency, recently, the Power-Class 2 (PC2) High Power User Equipment (HPUE) applied to B41 is deployed. To support HPUE, RF transmitters (TXs) need to deliver higher output power while maintaining stringent linearity requirements of emission mask, especially for third-order Counter Intermodulation (CIM3) in one Resource Block (1RB) case. CIM3 can be improved by several techniques such as power mixers [1,2], Harmonic-Reject Mixers (HRM) [3], notch-filter mixers [4, 5] and digital TXs [6]. Power-mixer, HRM and digital TX solutions may not be suitable for HPUE due to power-efficiency limitations. The notch-filter mixer is based on a voltage-mode passive mixer with 25%-duty-cycle LO, and it reduces 3flo, which exactly corresponds to the component at 3flo-fbb, by employing an LC trap. However, the conventional series [4] or parallel [5] 3flo trap causes a significant insertion loss at flo, which exactly corresponds to the component at flo+fbb, due to the trade-off between its efficiency, 3flo suppression and tuning range. This work presents a new transformer-based notch filter mixer. In this structure, the 3flo suppression can automatically track the channel frequency resulting in a wide operation frequency range of 1.4GHz to 2.7GHz while both the power efficiency and 3flo suppression are improved compared with the conventional notch-filter mixer [4,5].

This paper presents a wideband transformer-coupled CMOS power amplifier (PA). On-chip transmission-line transformers are used as key components of matching networks at output, input, and interstage. The wideband on-chip transformer is harnessed without any additional inductive devices so that a wideband power characteristic can be achieved. The PA is fabricated using a 0.18-μm CMOS process. It provides a saturated output power of 21.5 dBm with the power-added efficiency (PAE) of 20.3%, and the output 1-dB gain-compressed power (P1 dB) is 20.2 dBm with the PAE of 14.8% at 9.5 GHz, respectively. The small-signal gain is 25.3 dB and the 3-dB bandwidth is 6.5 GHz (6.5-13 GHz). The die area is 1.34 mm × 0.47 mm. Among the reported X/Ku-band CMOS PAs, this amplifier achieves the highest figure of merit, and also shows suitable performances for phased-array systems.

In this paper we report a 2.4 GHz low-power receiver front-end using current-reused folded-cascode scheme. Two fully integrated receiver front-ends are presented as a proof of concept. A conventional merged LNA and single-balanced (SB) mixer shows a conversion gain of 20.4 dB and a noise figure of 19 dB at 10 MHz intermediate frequency (IF), taking 500 /spl mu/A bias current from 1.0 V power supply. The proposed front-end achieves a conversion gain of 30.5 dB and a noise figure of 10.2 dB at 10MHz IF with the same power consumption of 500 /spl mu/W. The front-ends performances are compared with the previously reported low-power front-ends operating at similar frequency.

For the first time, low noise distributed oscillators for millimeter wave signal generation have been realized by using fully IC compatible, monolithically-integrable 3-D RF MEMS transmission lines. The active core circuits of the distributed oscillators have been fabricated using 0.18 /spl mu/m CMOS processes. On the top of this CMOS circuits, low-loss MEMS transmission lines have been monolithically integrated suspending by 25 /spl mu/m. Phase noise of the fabricated MEMS distributed oscillators has been measured as -125.7 dBc/Hz at 1 MHz offset frequency from oscillation frequency of 13 GHz. This is the lowest phase noise ever reported on distributed oscillators implemented in CMOS technology.

In this paper, we report the performance comparison of 5 GHz CMOS VCOs fabricated by 0.18 /spl mu/m six-metal mixed-mode RF CMOS processes with respect to the same VCOs integrated with high Q MEMS inductors. The CMOS inductors implemented by a top-level 2 /spl mu/m-thick Al/Cu metal layer typically show Q factors of about 10, while the MEMS inductors can give much higher Q factors over 25. Differential CMOS VCO circuits have been optimally designed for the respective Q factors of both CMOS and MEMS inductors. Phase noise has been measured and compared for the fabricated VCOs, demonstrating that the VCOs with MEMS inductors can give better phase noise by more than 7 dB in the offset frequency range from 30 kHz to 3 MHz.