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We present a 16-Gb/s transmitter composed of a stacked voltage-mode CMOS driver and periodic-loaded reverse biased pn junction Mach–Zehnder modulator. The transmitter shows 9-dB extinction ratio and 10.3-pJ/bit power consumption and operates with 1.3 μm light. Penalties as low as 0.5 dB were seen as compared to a 25-Gb/s LiNbO3 transmitter with both a monolithic metal–semiconductor–metal receiver and a reference receiver at 16-Gb/s operation. We also present an analytic expression for relative transmitter penalty (RTP), which allows one to quickly assess the system impact of design parameters such as peak-to-peak modulator drive voltage, modulator figure of merit, and transmitter extinction ratio to determine the circumstances under which a stacked CMOS cascode driver is desirable.

We demonstrate 4 × 4 and 8 × 8 switch fabrics in multistage topologies based on 2 × 2 Mach-Zehnder interferometer switching elements. These fabrics are integrated onto a single chip with digital CMOS logic, device drivers, thermo-optic phase tuners, and electro-optic phase modulators using IBM's 90 nm silicon integrated nanophotonics technology. We show that the various switch-and-driver systems are capable of delivering nanosecond-scale reconfiguration times, low crosstalk, compact footprints, low power dissipations, and broad spectral bandwidths. Moreover, we validate the dynamic reconfigurability of the switch fabric changing the state of the fabric using time slots with sub-100-ns durations. We further verify the integrity of high-speed data transfers under such dynamic operation. This chip-scale switching system technology may provide a compelling solution to replace some routing functionality currently implemented as bandwidth- and power-limited electronic switch chips in high-performance computing systems.

A manufacturable platform of CMOS, RF and opto-electronic devices fully PDK enabled to demonstrate a 4×25 Gb/s reference design is presented. With self-aligned fiber attach, this technology enables low-cost O-band data-com transceivers. In addition, this technology can offer enhanced performance and yield in hybrid-assembly for applications at 25 Gbaud and beyond.

We present a 20 Gb/s monolithically integrated transmitter with stacked CMOS driver and periodic-loaded PN-junction Mach-Zehnder modulator (MZM) fabricated in IBM’s sub-100nm technology node. Transmitter extinction ratios of 10 dB at 20 Gb/s are demonstrated.

A silicon microring modulator with independent resonance and coupling tunability is monolithically integrated with a stacked CMOS driver. At 25Gbps, the OMA is -1.9dBm, the extinction ratio is 3.5dB, and the excess loss is 2.6dB.

A single-die monolithically integrated multichannel silicon nanophotonics receiver is fabricated in IBM 90nm CMOS Nanophotonics technology node. Electrical eye diagrams for 16 channels exhibit open eyes up to 20Gbps with a 127mW/channel power efficiency.

A monolithically-integrated germanium receiver is fabricated in the IBM's newly established 90nm CMOS-integrated nanophotonics technology node. Technology is promising for cost-effective 10Gbps to 28Gbps optical communications links operating within extended temperature range up to 95°C.

A sub-100nm technology that allows the monolithic integration of optical devices as features into a 90nm base high-performance logic technology node is demonstrated. The technology is promising for next generation optical communications for applications.

We demonstrate a 1×2 ring resonator switch and a 2×2 Mach Zehnder switch, monolithically integrated with digital CMOS drivers in IBM's proprietary 90-nm photonics-enabled CMOS process. Static and dynamic performance metrics are characterized.

We demonstrate in a single chip a complete multiport photonic switching system using IBM 90-nm photonics-enabled CMOS. The system includes CMOS logic, switch drivers, multistage 4×4 and 8×8 photonic switch fabrics, and thermo-optic phase tuners.

The first sub-100nm technology that allows the monolithic integration of optical modulators and germanium photodetectors as features into a current 90nm base highperformance logic technology node is demonstrated. The resulting 90nm CMOS-integrated Nano-Photonics technology node is optimized for analog functionality to yield power-efficient single-die multichannel wavelength-mulitplexed 25Gbps transceivers.