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This article presents CMOS power amplifiers for WLAN applications. These power amplifiers use current and voltage combining techniques for simultaneous improvement of the output power and efficiency, respectively, and are analyzed to determine which technique is more suitable for WLAN applications. The power amplifiers are fabricated with a 180 nm CMOS process. Their performance is verified using an 802.11 g modulated signal with 64 QAM, 20 MHz of bandwidth, and 54‐Mbps at 2.7 GHz. The measurements of the current and voltage combining power amplifiers show about 21.9 and 21.8 dBm of average output power, respectively, at −25 dB error vector magnitude (EVM), and about 20.2 and 18 dBm of average output power, respectively, at −30 dB EVM for a commercial specification. In addition, the current combining PA is operated in a multi‐mode manner, which saves the power stage current about 225 mA of the power stage current at low power mode. No pre‐distortion technique is required and all components are integrated on the chip. [ABSTRACT FROM AUTHOR]

In this paper, a CMOS antiphase power amplifier (PA) is presented with a multigate transistor (MGTR) technique that improves its linearity. The drive stage of the PA is biased in the subthreshold region, such as in class C, to realize the antiphase technique. The nonlinearity of the power stage of the PA is canceled out using the third-order intermodulation distortion and phase distortion of the drive stage. The cancellation effect is further optimized and enhanced without any performance degradation with the aid of the proposed MGTR technique at the drive stage. Unlike the traditional technique, which suppresses the nonlinearity of the PA, the MGTR technique is used to enhance the nonlinearity of the drive stage to cancel out the significant nonlinearity of the power stage. The proposed PA is fabricated with a 180-nm RF CMOS process and used to verify the linearity by WCDMA and LTE signals. The measurement results show an average output power of 25.8 dBm, PAE of 28%, and error vector magnitude of 3% at 1.85 GHz for the WCDMA. The PA also shows an average output power of 24.4–25.8 dBm at 1.7–2.0 GHz for the WCDMA. The PA is verified for LTE signals with 10 MHz of bandwidth/16 QAM and with 20 MHz of bandwidth/64 QAM. No digital predistortion or off-chip components are utilized. [ABSTRACT FROM PUBLISHER]

In this study, we design a differential power amplifier using a 110-nm RF CMOS process. To improve amplifier gain, we propose an active balun as a driver stage of the power amplifier. The passive input balun is removed to minimize the substrate loss. In the proposed power amplifier structure, the active balun converts a single-ended signal into a differential signal and at the same time provides sufficient gain as the driver stage of the power stage. To verify the feasibility of the proposed power amplifier structure, we designed a typical and the proposed power amplifier using identical processes and with the same design parameters, except for the driver stage and the input transformer of the typical power amplifier. The measured improvement of the gain of the proposed power amplifier is approximately 4.2 dB compared to that of the typical power amplifier. From the measured results, we successfully prove the feasibility of the proposed power amplifier. [ABSTRACT FROM AUTHOR]

ABSTRACT This article describes a highly efficient X-band CMOS power amplifier. To obtain high drain voltage for high power, instead of using the typical cascode structure, we use a common-source structure with a long channel length transistor. Generally, to enable high operating speed at high frequency, smaller transistor technology is used, but we demonstrate that using large transistor technology is also possible. The proposed power amplifier is designed with transistors of 300-nm channel length in a common-source structure using a differential structure of RFCMOS technology. Consequently, the maximum output power is 19 dBm with a power added efficiency of 40.5% at an input power of 5 dBm. This RFCMOS power amplifier includes all matching circuits and biasing circuits, and no external components are required. © 2014 Wiley Periodicals, Inc. Microwave Opt Technol Lett 56:2552-2557, 2014 [ABSTRACT FROM AUTHOR]

ABSTRACT In this work, we analyzed the efficiency of a switching-mode RF CMOS power amplifier with the following design parameters: the on resistance and the parasitic capacitance of the power transistor. The power amplifier is composed of a class-D type driver stage and a class-E type power stage. The power consumption of the driver stage, the load impedance of the power stage, and the loss of the output matching networks are considered for a numerical analysis. We investigated the normalized drain efficiency according to the variable supply voltage of the power stage for polar transmitter applications. From the simulated results of the power amplifier, we successfully proved the feasibility of using the numerical analysis. The designed power amplifier is implemented using 0.13 μm RF CMOS process to verify the numerical results by means of an experiment. A distributed active transformer is used for an output matching network. © 2014 Wiley Periodicals, Inc. Microwave Opt Technol Lett 56:110-117, 2014 [ABSTRACT FROM AUTHOR]