Search

Monolithic active pixel sensors (MAPS) produced in a 65 nm CMOS imaging technology are being investigated for applications in particle physics. The MAPS design has a small collection electrode characterized by an input capacitance of ∼ fF, granting a high signal-to-noise ratio and low power consumption. Additionally, the 65 nm CMOS imaging technology brings a reduction in material budget and improved logic density of the readout circuitry, compared to previously studied technologies. Given these features, this technology was chosen by the TANGERINE project to develop the next generation of silicon pixel sensors. The sensor design targets temporal and spatial resolutions compatible with the requirements for a vertex detector at future lepton colliders. Simulations and test-beam characterization of technology demonstrators have been carried out in close collaboration with the CERN EP R&D program and the ALICE ITS3 upgrade. TCAD device simulations using generic doping profiles and Monte Carlo simulations have been used to build an understanding of the technology and predict the performance parameters of the sensor. Technology demonstrators of a 65 nm CMOS MAPS with a small collection electrode have been characterized in laboratory and test-beam facilities by studying performance parameters such as cluster size, charge collection, and efficiency. This work compares simulation results to test-beam data. The experimental results establish this technology as a promising candidate for a vertex detector at future lepton colliders and give valuable information for improving the simulation approach. [ABSTRACT FROM AUTHOR]

A new generation of Monolithic Active Pixel Sensors (MAPS), produced in a 65 nm CMOS imaging process, promises higher densities of on-chip circuits and, for a given pixel size, more sophisticated in-pixel logic compared to larger feature size processes. MAPS are a cost-effective alternative to hybrid pixel sensors since flip-chip bonding is not required. In addition, they allow for significant reductions of the material budget of detector systems, due to the smaller physical thicknesses of the active sensor and the absence of a separate readout chip. The TANGERINE project develops a sensor suitable for future Higgs factories as well as for a beam telescope to be used at beam-test facilities. The sensors will have small collection electrodes (order of µm) to maximize the signal-to-noise ratio, which makes it possible to minimize power dissipation in the circuitry. The first batch of test chips, featuring full front-end amplifiers with Krummenacher feedback, was produced and tested at the Mainzer Mikrotron (MAMI) at the end of 2021. MAMI provides an electron beam with currents up to 100 µA and an energy of 855 MeV. The analog output signal of the test chips was recorded with a high bandwidth oscilloscope and used to study the charge-sensitive amplifier of the chips in terms of waveform analysis. A beam telescope was used as a reference system to allow for track-based analysis of the recorded data. [ABSTRACT FROM AUTHOR]

The Tangerine project aims to develop new state-of-the-art high-precision silicon detectors. Part of the project has the goal of developing a monolithic active pixel sensor using a novel 65 nm CMOS imaging process, with a small collection electrode. This is the first application of this process in particle physics, and it is of great interest as it allows for an increased logic density and reduced power consumption and material budget compared to other processes. The process is envisioned to be used in for example the next ALICE inner tracker upgrade, and in experiments at the electron-ion collider. The initial goal of the three-year Tangerine project is to develop and test a sensor in a 65 nm CMOS imaging process that can be used in test beam telescopes at DESY, providing excellent spatial resolution and high time resolution, and thus demonstrating the capabilities of the process. The project covers all aspects of sensor R&D, from electronics and sensor design using simulations, to prototype test chip characterisation in labs and at test beams. The sensor design simulations are performed by using a powerful combination of detailed electric field simulations using technology computer-aided design and high-statistics Monte Carlo simulations using the Allpix 2 framework. A first prototype test chip in the process has been designed and produced, and successfully operated and tested both in labs and at test beams. [ABSTRACT FROM AUTHOR]